11 Commits (a9526bab8f825f40b658c82054ee67de887ebcd5)

Author	SHA1	Message	Date
David Garske	a9526bab8f	STM32 QSPI Flash support. Refactor SPI to allow different GPIO base/AF for each pin. Adds `DEBUG_UART` support for H7.	2022-12-20 13:31:28 +01:00
David Garske	62132201bf	Peer review feedback. Rename secure boot function and move build option macro around function.	2021-11-29 23:17:43 -08:00
David Garske	cf15e71796	Fix indent and line length.	2021-11-29 23:17:43 -08:00
David Garske	d2f762c8eb	Improve the SEC_SIZE check and add build option to disable check. Add TODO note.	2021-11-29 23:17:43 -08:00
David Garske	905730d927	Fixes for secure user memory feature.	2021-11-29 23:17:43 -08:00
David Garske	2526dbb40a	Fix to use flash base address on STM32G0.	2021-11-29 23:17:43 -08:00
David Garske	56174581c6	Secure boot support (experimental)	2021-11-29 23:17:43 -08:00
David Garske	d38de3b432	Update copyright year	2021-07-19 07:50:02 -07:00
Chris Conlon	1f57ad9f39	update copyright to 2020	2020-01-03 15:36:00 -08:00
David Garske	f2be454e08	Fixes for building STM32G0.	2019-07-16 12:04:34 -07:00
Daniele Lacamera	254882c5f2	Added support for STM32G0 (tested on STM32G070-Nucleo)	2019-07-16 08:46:14 -07:00