mirror of https://github.com/wolfSSL/wolfBoot.git
85 lines
3.9 KiB
Markdown
85 lines
3.9 KiB
Markdown
# Xilinx SDK wolfBoot Project
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To use this example project:
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1. Copy `.cproject` and `.project` into the wolfBoot root.
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2. From the Xilinx SDK Import wolfBoot using "Import" -> "Existing Projects into Workspace".
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## Xilinx SDK BSP
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This project uses a BSP named `standalone_bsp_0`, which must be configured to use "hypervisor guest" in the BSP configuration settings. This will enable the EL-1 support required with Bl31 (ARM Trusted Firmware). The BSP generates a include/bspconfig.h, which should have these defines set:
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```
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#define EL1_NONSECURE 1
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#define HYP_GUEST 1
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```
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Note: This is a generated file from the BSP configurator tool, which is edited by opening the `system.mss` file.
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## wolfBoot Configuration
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A build settings template for Zynq UltraScale+ can be found here `./config/examples/zynqmp.config`. This file can be copied to wolfBoot root as `.config` for building from the command line. These template settings are also in this `.cproject` as preprocessor macros. These settings are loaded into the `target.h.in` template by the wolfBoot `make`. If not using the built-in make then the following defines will need to be manually created in `target.h`:
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```
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#define WOLFBOOT_SECTOR_SIZE 0x20000
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#define WOLFBOOT_PARTITION_BOOT_ADDRESS 0x800000
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#define WOLFBOOT_LOAD_ADDRESS 0x10000000
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#define WOLFBOOT_PARTITION_SIZE 0x2A00000
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#define WOLFBOOT_PARTITION_UPDATE_ADDRESS 0x3A00000
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#define WOLFBOOT_PARTITION_SWAP_ADDRESS 0x63E0000
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#define WOLFBOOT_DTS_BOOT_ADDRESS 0x7E0000
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#define WOLFBOOT_DTS_UPDATE_ADDRESS 0x39E0000
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#define WOLFBOOT_LOAD_DTS_ADDRESS 0x11800000
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```
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Note: If not using Position Independent Code (PIC) the linker script `ldscript.ld` must have the start address offset to match the `WOLFBOOT_LOAD_ADDRESS`.
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## Signing Example
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```sh
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python3 ./tools/keytools/sign.py --rsa4096 --sha3 ../helloworld/Debug/helloworld.elf ./rsa4096.der 1
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```
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## Bootgen
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Xilinx uses a `bootgen` tool for generating a boot binary image that has Xilinx headers, which the FSBL (First Stage Boot Loader) understands. See the `boot.bif` and `boot_auth.bif` as examples.
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* Use "partition_owner=uboot" to prevent a partition from being loaded into RAM.
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* Use "offset=" option to place the application into a specific location in flash.
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* Use "load=" option to have FSBL load into specific location in RAM.
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### Adding RSA Authentication
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1. Generate keys:
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* `bootgen.exe -generate_keys auth pem -arch zynqmp -image boot.bif`
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2. Create hash for primary key:
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* `bootgen.exe -image boot.bif -arch zynqmp -w -o i BOOT.BIN -efuseppkbits ppkf_hash.txt`
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3. Import example project for programming eFuses:
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* New BSP project (program efuses , ZCU102_hw_platform, standalone, CPU: PSU_cortexa53_0)
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* Goto Xilinx Board Support Packet Settings.
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* Scroll down to Supported Libraries and Check the xiskey libray
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* In the system.mss pane, scroll down to Libraries and click Import Examples.
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* Check the xilskey_esfuseps_zynqmp_example
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4. Edit `xilskey_efuseps_zynqmp_input.h`
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* 433 `#define XSK_EFUSEPS_WRITE_PPK0_HASH TRUE`
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* 453 `#define XSK_EFUSEPS_PPK0_IS_SHA3 TRUE`
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* 454 `#define XSK_EFUSEPS_PPK0_HASH "0000000000000000000000000000000000000000000000000000000000000000" /* from ppkf_hash.txt */``
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5. Update boot.bif (see boot_auth.bif)
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```
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[auth_params] ppk_select=0; spk_id=0x00000000
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[pskfile] pskf.pem
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[sskfile] sskf.pem
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authentication=rsa
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```
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6. Build “boot.bin” image:
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* `bootgen.exe -image boot.bif -arch zynqmp -o i BOOT.BIN -w`
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Note: To generate a report of a boot.bin use the `bootgen_utility`:
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`bootgen_utility -arch zynqmp -bin boot.bin -out boot.bin.txt`
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### References:
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* [ZAPP1319](https://www.xilinx.com/support/documentation/application_notes/xapp1319-zynq-usp-prog-nvm.pdf): Programming BBRAM and eFUSEs
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* [UG1283](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug1283-bootgen-user-guide.pdf): Bootgen User Guide
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