mirror of https://github.com/wolfSSL/wolfBoot.git
228 lines
6.8 KiB
C
228 lines
6.8 KiB
C
/* riscv.h
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*
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* Copyright (C) 2026 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#ifndef RISCV_H
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#define RISCV_H
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/* RISC-V privilege mode:
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* M-mode (direct boot from eNVM): WOLFBOOT_RISCV_MMODE
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* S-mode (running under HSS/SBI): default
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*/
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#ifndef WOLFBOOT_STACK_TOP
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#ifdef WOLFBOOT_RISCV_MMODE
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#define WOLFBOOT_STACK_TOP 0x0A040000 /* end of L2 Scratchpad (256KB) */
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#else
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#define WOLFBOOT_STACK_TOP 0x80200000 /* DDR */
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#endif
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#endif
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/* XLEN-dependent load/store mnemonics and register width */
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#if __riscv_xlen == 64
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#define STORE sd
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#define LOAD ld
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#define REGBYTES 8
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#define VECTOR_ALIGN 3
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#else
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#define STORE sw
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#define LOAD lw
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#define REGBYTES 4
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#define VECTOR_ALIGN 2
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#endif
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/* S-mode timer frequency (1 MHz default; platform may override).
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* In M-mode, hal_get_timer() returns mcycle so the platform (e.g. mpfs250.h)
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* sets RISCV_SMODE_TIMER_FREQ to the CPU clock; do not default it here. */
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#if !defined(WOLFBOOT_RISCV_MMODE) && !defined(RISCV_SMODE_TIMER_FREQ)
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#define RISCV_SMODE_TIMER_FREQ 1000000
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#endif
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/* Mode-prefixed CSR name helper */
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#ifdef WOLFBOOT_RISCV_MMODE
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#define MODE_PREFIX(__suffix) m##__suffix
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#else
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#define MODE_PREFIX(__suffix) s##__suffix
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#endif
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/* CSR access macros */
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#define csr_read(csr) \
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({ \
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register unsigned long __v; \
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__asm__ __volatile__ ("csrr %0, " #csr : "=r"(__v) : ); \
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__v; \
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})
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#define csr_write(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrw " #csr ", %0" : : "rK"(__v)); \
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})
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#define csr_set(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrs " #csr ", %0" : : "rK"(__v)); \
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})
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#define csr_clear(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrc " #csr ", %0" : : "rK"(__v)); \
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})
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#ifndef __ASSEMBLER__
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static inline void riscv_icache_sync(void)
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{
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#ifdef __riscv_zifencei
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__asm__ __volatile__("fence.i" ::: "memory");
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#endif
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}
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#endif
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/* Interrupt numbers (for MIE/MIP/SIE/SIP registers) */
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#define IRQ_S_SOFT 1
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#define IRQ_M_SOFT 3
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#define IRQ_S_TIMER 5
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#define IRQ_M_TIMER 7
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#define IRQ_S_EXT 9
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#define IRQ_M_EXT 11
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/* Privilege levels */
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#define PRV_S 1
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#define PRV_M 3
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/* MSTATUS register bits */
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#define MSTATUS_SIE (1UL << 1)
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#define MSTATUS_MIE (1UL << 3)
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#define MSTATUS_SPIE (1UL << 5)
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#define MSTATUS_MPIE (1UL << 7)
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#define MSTATUS_SPP (1UL << 8)
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#define MSTATUS_MPP_SHIFT 11
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#define MSTATUS_MPP_MASK (3UL << MSTATUS_MPP_SHIFT)
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#define MSTATUS_MPP_M (PRV_M << MSTATUS_MPP_SHIFT)
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#define MSTATUS_MPP_S (PRV_S << MSTATUS_MPP_SHIFT)
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/* SSTATUS bits (S-mode visible subset) */
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#define SSTATUS_SIE (1UL << 1)
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#define SSTATUS_SPIE (1UL << 5)
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/* MIP register bits (mip CSR: pending interrupt flags, written by hardware) */
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#define MIP_MSIP (1 << IRQ_M_SOFT)
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/* MIE register bits (mie CSR: interrupt enable, always written by software.
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* Bit positions match MIP but use these names when targeting the mie register
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* to avoid confusing the two CSRs.) */
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#define MIE_MSIE (1 << IRQ_M_SOFT)
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#define MIE_MTIE (1 << IRQ_M_TIMER)
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#define MIE_MEIE (1 << IRQ_M_EXT)
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/* SIE register bits */
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#define SIE_SSIE (1 << IRQ_S_SOFT)
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#define SIE_STIE (1 << IRQ_S_TIMER)
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#define SIE_SEIE (1 << IRQ_S_EXT)
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/* MCAUSE / SCAUSE interrupt bit and exception code mask */
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#if __riscv_xlen == 64
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#define MCAUSE_INT 0x8000000000000000ULL
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#define MCAUSE_CAUSE 0x7FFFFFFFFFFFFFFFULL
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#else
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#define MCAUSE_INT 0x80000000UL
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#define MCAUSE_CAUSE 0x7FFFFFFFUL
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#endif
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/* PLIC - Platform-Level Interrupt Controller
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* Generic implementation, enabled when platform defines PLIC_BASE.
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*
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* Standard memory map offsets:
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* 0x000000: Priority registers (1 word/source)
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* 0x002000: Enable bits (per context, 1 bit/source)
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* 0x200000: Context registers (threshold + claim/complete per context)
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*
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* Platform must define PLIC_BASE (and optionally PLIC_NUM_SOURCES). */
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#define PLIC_PRIORITY_OFFSET 0x000000UL
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#define PLIC_ENABLE_OFFSET 0x002000UL
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#define PLIC_ENABLE_STRIDE 0x80UL
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#define PLIC_CONTEXT_OFFSET 0x200000UL
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#define PLIC_CONTEXT_STRIDE 0x1000UL
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#define PLIC_PRIORITY_DISABLED 0
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#define PLIC_PRIORITY_MIN 1
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#define PLIC_PRIORITY_MAX 7
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#define PLIC_PRIORITY_DEFAULT 4
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#ifndef __ASSEMBLER__
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#define PLIC_PRIORITY_REG(base, irq) \
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(*((volatile uint32_t*)((base) + PLIC_PRIORITY_OFFSET + ((irq) * 4))))
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#define PLIC_ENABLE_REG(base, ctx, irq) \
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(*((volatile uint32_t*)((base) + PLIC_ENABLE_OFFSET + \
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((ctx) * PLIC_ENABLE_STRIDE) + (((irq) / 32) * 4))))
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#define PLIC_ENABLE_BIT(irq) (1U << ((irq) % 32))
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#define PLIC_THRESHOLD_REG(base, ctx) \
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(*((volatile uint32_t*)((base) + PLIC_CONTEXT_OFFSET + \
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((ctx) * PLIC_CONTEXT_STRIDE) + 0x00)))
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#define PLIC_CLAIM_REG(base, ctx) \
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(*((volatile uint32_t*)((base) + PLIC_CONTEXT_OFFSET + \
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((ctx) * PLIC_CONTEXT_STRIDE) + 0x04)))
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#define PLIC_COMPLETE_REG(base, ctx) PLIC_CLAIM_REG(base, ctx)
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#endif /* !__ASSEMBLER__ */
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/* PLIC function declarations (boot_riscv.c, when PLIC_BASE is defined).
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* Platform must provide plic_get_context() and plic_dispatch_irq(). */
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#if defined(PLIC_BASE) && !defined(__ASSEMBLER__)
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#include <stdint.h>
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/* Platform-provided: Get PLIC context ID for current hart
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* Returns the context number (e.g., hart 1 S-mode = context 2) */
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extern uint32_t plic_get_context(void);
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void plic_set_priority(uint32_t irq, uint32_t priority);
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void plic_enable_interrupt(uint32_t irq);
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void plic_disable_interrupt(uint32_t irq);
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void plic_set_threshold(uint32_t threshold);
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uint32_t plic_claim(void);
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void plic_complete(uint32_t irq);
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extern void plic_dispatch_irq(uint32_t irq);
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#endif /* PLIC_BASE && !__ASSEMBLER__ */
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/* CLINT - Core Local Interruptor (M-mode only).
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* Provides software IPIs (MSIP) and timer (MTIME/MTIMECMP). */
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#ifdef WOLFBOOT_RISCV_MMODE
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#ifndef CLINT_BASE
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#define CLINT_BASE 0x02000000UL
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#endif
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#define CLINT_MSIP_OFFSET 0x0000UL
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#ifndef __ASSEMBLER__
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#define CLINT_MSIP(hart) \
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(*((volatile uint32_t*)(CLINT_BASE + CLINT_MSIP_OFFSET + ((hart) * 4))))
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#endif
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#endif /* WOLFBOOT_RISCV_MMODE */
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#endif /* RISCV_H */
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