mirror of https://github.com/wolfSSL/wolfBoot.git
149 lines
4.5 KiB
C
149 lines
4.5 KiB
C
/* uart_drv_stm32wb.c
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*
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* Driver for the back-end of the UART_FLASH module.
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*
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* Example implementation for stm32WB, using UART1.
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*
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* Pinout: RX=PB7, TX=PB6 (VCOM port UART1 -> STLINK USB)
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*
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* Copyright (C) 2021 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#ifdef TARGET_stm32wb
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#include <stdint.h>
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/* Driver hardcoded to work on UART1 (PB6/PB7) */
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#define UART1 (0x40013800)
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#define UART1_PIN_AF 7
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#define UART1_RX_PIN 7
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#define UART1_TX_PIN 6
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#define UART1_CR1 (*(volatile uint32_t *)(UART1 + 0x00))
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#define UART1_CR2 (*(volatile uint32_t *)(UART1 + 0x04))
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#define UART1_BRR (*(volatile uint32_t *)(UART1 + 0x0C))
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#define UART1_ISR (*(volatile uint32_t *)(UART1 + 0x1C))
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#define UART1_RDR (*(volatile uint32_t *)(UART1 + 0x24))
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#define UART1_TDR (*(volatile uint32_t *)(UART1 + 0x28))
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#define UART_CR1_UART_ENABLE (1 << 0)
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#define UART_CR1_TX_ENABLE (1 << 3)
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#define UART_CR1_RX_ENABLE (1 << 2)
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#define UART_CR1_SYMBOL_LEN (1 << 28)
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#define UART_CR1_FIFO_ENABLE (1 << 29)
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#define UART_CR1_PARITY_ENABLED (1 << 10)
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#define UART_CR1_PARITY_ODD (1 << 9)
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#define UART_ISR_TX_EMPTY (1 << 7)
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#define UART_ISR_RX_NOTEMPTY (1 << 5)
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#define CLOCK_SPEED (64000000) /* 64 MHz (STM32WB55) */
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#define APB2_CLOCK_ER (*(volatile uint32_t *)(0x58000060))
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#define UART1_APB2_CLOCK_ER_VAL (1 << 14)
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#define AHB2_CLOCK_ER (*(volatile uint32_t *)(0x5800004c))
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#define GPIOB_AHB2_CLOCK_ER (1 << 1)
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#define GPIOB_BASE 0x48000400
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#define GPIOB_MODE (*(volatile uint32_t *)(GPIOB_BASE + 0x00))
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#define GPIOB_AFL (*(volatile uint32_t *)(GPIOB_BASE + 0x20))
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#define GPIOB_AFH (*(volatile uint32_t *)(GPIOB_BASE + 0x24))
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#define GPIO_MODE_AF (2)
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static void uart_pins_setup(void)
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{
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uint32_t reg;
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AHB2_CLOCK_ER |= GPIOB_AHB2_CLOCK_ER;
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/* Set mode = AF */
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reg = GPIOB_MODE & ~ (0x03UL << (UART1_RX_PIN * 2));
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GPIOB_MODE = reg | (2 << (UART1_RX_PIN * 2));
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reg = GPIOB_MODE & ~ (0x03UL << (UART1_TX_PIN * 2));
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GPIOB_MODE = reg | (2 << (UART1_TX_PIN * 2));
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/* Alternate function: use low pins (6 and 7) */
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reg = GPIOB_AFL & ~(0xfUL << ((UART1_TX_PIN) * 4));
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GPIOB_AFL = reg | (UART1_PIN_AF << ((UART1_TX_PIN) * 4));
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reg = GPIOB_AFL & ~(0xfUL << ((UART1_RX_PIN) * 4));
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GPIOB_AFL = reg | (UART1_PIN_AF << ((UART1_RX_PIN) * 4));
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}
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int uart_tx(const uint8_t c)
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{
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uint32_t reg;
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do {
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reg = UART1_ISR;
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} while ((reg & UART_ISR_TX_EMPTY) == 0);
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UART1_TDR = c;
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return 1;
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}
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int uart_rx(uint8_t *c)
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{
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volatile uint32_t reg = UART1_ISR;
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if ((reg & UART_ISR_RX_NOTEMPTY) != 0) {
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reg = UART1_RDR;
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*c = (uint8_t)(reg & 0xff);
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return 1;
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}
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return 0;
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}
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int uart_init(uint32_t bitrate, uint8_t data, char parity, uint8_t stop)
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{
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uint32_t reg;
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/* Enable pins and configure for AF7 */
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uart_pins_setup();
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/* Turn on the device */
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APB2_CLOCK_ER |= UART1_APB2_CLOCK_ER_VAL;
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UART1_CR1 &= ~(UART_CR1_UART_ENABLE);
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UART1_CR1 &= ~(UART_CR1_FIFO_ENABLE);
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/* Configure for TX + RX */
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UART1_CR1 |= (UART_CR1_TX_ENABLE | UART_CR1_RX_ENABLE);
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/* Configure clock */
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UART1_BRR = CLOCK_SPEED / (2 * bitrate);
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/* Configure data bits */
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if (data == 8)
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UART1_CR1 &= ~UART_CR1_SYMBOL_LEN;
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else
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UART1_CR1 |= UART_CR1_SYMBOL_LEN;
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/* Configure parity */
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switch (parity) {
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case 'O':
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UART1_CR1 |= UART_CR1_PARITY_ODD;
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/* fall through to enable parity */
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/* FALL THROUGH */
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case 'E':
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UART1_CR1 |= UART_CR1_PARITY_ENABLED;
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break;
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default:
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UART1_CR1 &= ~(UART_CR1_PARITY_ENABLED | UART_CR1_PARITY_ODD);
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}
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/* Set stop bits (not supported) */
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(void)stop;
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/* Turn on uart */
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UART1_CR1 |= UART_CR1_UART_ENABLE;
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return 0;
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}
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#endif /* TARGET_stm32wb */
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