mirror of https://github.com/wolfSSL/wolfBoot.git
534 lines
21 KiB
Markdown
534 lines
21 KiB
Markdown
# Xilinx SDK wolfBoot Project
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To use this example project:
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1. Copy `.cproject` and `.project` into the wolfBoot root.
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2. From the Xilinx SDK Import wolfBoot using "Import" -> "Existing Projects into Workspace".
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## Xilinx SDK BSP
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This project uses a BSP named `standalone_bsp_0`, which must be configured to use "hypervisor guest" in the BSP configuration settings, which is edited by opening the `platform.spr` file under "standalone on psa_cortexa53_0" -> "Board Support Package" -> "Modify BSP Settings".
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This will enable the EL-1 support required with Bl31 (ARM Trusted Firmware). The BSP generates a `include/bspconfig.h`, which should have these defines set:
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```
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#define EL1_NONSECURE 1
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#define HYP_GUEST 1
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```
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You may need to adjust/add the following project settings under Properties -> C/C++ General:
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1) Platform bspInclude path: "Paths and Symbols" -> "Includes" -> "GNU C" -> "Add" -> Workspace Path for platform (example: `/zcu102/export/zcu102/sw/zcu102/standalone_domain/bspinclude/include`).
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2) Platform BSP Library path: See "Library Paths" -> "Add" (example: `/zcu102/psu_cortexa53_0/standalone_domain/bsp/psu_cortexa53_0/lib`).
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## wolfBoot Configuration
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A build settings template for Zynq UltraScale+ can be found here `./config/examples/zynqmp.config`. This file can be copied to wolfBoot root as `.config` for building from the command line.
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```sh
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$ cp ./config/examples/zynqmp.config .config
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$ make keytools
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```
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These template settings are also in this `.cproject` as preprocessor macros. These settings are loaded into the `target.h.in` template by the wolfBoot `make`. If not using the built-in make then the following defines will need to be manually created in `target.h`:
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```
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#define WOLFBOOT_SECTOR_SIZE 0x20000
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#define WOLFBOOT_PARTITION_BOOT_ADDRESS 0x800000
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#define WOLFBOOT_LOAD_ADDRESS 0x10000000
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#define WOLFBOOT_PARTITION_SIZE 0x2A00000
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#define WOLFBOOT_PARTITION_UPDATE_ADDRESS 0x3A00000
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#define WOLFBOOT_PARTITION_SWAP_ADDRESS 0x63E0000
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#define WOLFBOOT_DTS_BOOT_ADDRESS 0x7E0000
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#define WOLFBOOT_DTS_UPDATE_ADDRESS 0x39E0000
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#define WOLFBOOT_LOAD_DTS_ADDRESS 0x11800000
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```
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The default .cproject build symbols are:
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```
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ARCH_AARCH64
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ARCH_FLASH_OFFSET=0x0
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CORTEX_A53
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DEBUG_ZYNQ=1
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EXT_FLASH=1
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FILL_BYTE=0xFF
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IMAGE_HEADER_SIZE=1024
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MMU
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NO_QNX
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NO_XIP
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PART_BOOT_EXT=1
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PART_SWAP_EXT=1
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PART_UPDATE_EXT=1
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TARGET_zynq
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WC_HASH_DATA_ALIGNMENT=8
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WOLFBOOT_ARCH_AARCH64
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WOLFBOOT_DUALBOOT
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WOLFBOOT_ELF
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WOLFBOOT_HASH_SHA3_384
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WOLFBOOT_ORIGIN=0x0
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WOLFBOOT_SHA_BLOCK_SIZE=4096
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WOLFBOOT_SIGN_RSA4096
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WOLFBOOT_UBOOT_LEGACY
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```
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Note: If not using Position Independent Code (PIC) the linker script `ldscript.ld` must have the start address offset to match the `WOLFBOOT_LOAD_ADDRESS`.
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## Zynq UltraScale+ ARMv8 Crypto Extensions
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By default the ARM assembly speedups for SHA will be enabled. This uses inline assembly in wolfcrypt/src/port/arm/ and the armb8 crypto extensions. To disable set `NO_ARM_ASM=1`.
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## Generate signing key
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The keygen tool creates an RSA 4096-bit private key (`wolfboot_signing_private_key.der`) and exports the public key to `src/keystore.c` for wolfBoot to use at compile-time as the default root-of-trust.
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```sh
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$ ./tools/keytools/keygen --rsa4096 -g wolfboot_signing_private_key.der
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Keytype: RSA4096
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Generating key (type: RSA4096)
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RSA public key len: 550 bytes
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Associated key file: wolfboot_signing_private_key.der
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Partition ids mask: ffffffff
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Key type : RSA4096
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Public key slot: 0
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Done.
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```
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## Signing Example
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```sh
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$ ./tools/keytools/sign --rsa4096 --sha3 ../hello_world/Debug/hello_world.elf ./wolfboot_signing_private_key.der 1
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wolfBoot KeyTools (Compiled C version)
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wolfBoot version 2020000
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Update type: Firmware
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Input image: ../hello_world/Debug/hello_world.elf
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Selected cipher: RSA4096
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Selected hash : SHA3
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Public key: ./wolfboot_signing_private_key.der
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Output image: ../hello_world/Debug/hello_world_v1_signed.bin
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Target partition id : 1
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Found RSA512 key
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image header size calculated at runtime (1024 bytes)
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Calculating SHA3 digest...
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Signing the digest...
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Output image(s) successfully created.
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```
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## Bootgen
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Xilinx uses a `bootgen` tool for generating a boot binary image that has Xilinx headers, which the FSBL (First Stage Boot Loader) understands. See the `boot.bif` and `boot_auth.bif` as examples.
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* Use "partition_owner=uboot" to prevent a partition from being loaded into RAM.
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* Use "offset=" option to place the application into a specific location in flash.
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* Use "load=" option to have FSBL load into specific location in RAM.
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Default install locations for bootgen tools:
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* Linux: `/tools/Xilinx/Vitis/2022.1/bin`
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* Windows: `C:\Xilinx\Vitis\2022.1\bin`
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Open the Vitis Shell from the IDE by using file menu "Xilinx" -> "Vitis Shell".
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Generating a boot.bin (from boot.bif).
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Example boot.bif in workspace root:
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```
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// Boot BIF example for wolfBoot with signed Hello World
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// Note: "partition_owner=uboot" prevents partition from being loaded to RAM
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the_ROM_image:
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{
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[bootloader, destination_cpu=a53-0] zcu102\zynqmp_fsbl\fsbl_a53.elf
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[destination_cpu=a53-0, exception_level=el-2] wolfboot\Debug\wolfboot.elf
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[destination_cpu=a53-0, partition_owner=uboot, offset=0x800000] hello_world\Debug\hello_world_v1_signed.bin
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}
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```
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You can use exception level 3, 2 or 1 depending on your needs. See hal/zynq.h options EL3_SECURE, EL2_HYPERVISOR and EL1_NONSECURE for enabled/disabling entry support for each. Default is support for EL2.
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From the workspace root:
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```sh
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bootgen -image boot.bif -arch zynqmp -w -o BOOT.bin
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****** Xilinx Bootgen v2022.1
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**** Build date : Apr 18 2022-16:02:32
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** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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[INFO] : Bootimage generated successfully
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```
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## Running Boot.bin
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* QSPI: Flash using Vitis -> Xilinx (menu) -> Program Flash
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* SD: or copy boot.bin to SDCARD
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| Boot Mode | MODE Pins 3:0 | Mode SW6[4:1] |
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| --------- | ------------- | -------------- |
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| JTAG | 0 0 0 0 | on, on, on, on |
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| QSPI32 | 0 0 1 0 | on, on, off,on |
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| SD | 1 1 1 0 | off,off,off,on |
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## Example boot output
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```
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wolfBoot Secure Boot
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Read FlashID Lower: Ret 0, 20 BB 20
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Read FlashID Upper: Ret 0, 20 BB 20
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Versions: Boot 1, Update 0
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Trying Boot partition at 800000
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Boot partition: 800000 (size 226024, version 0x1)
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info: LMS wolfBoot_verify_signature
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info: using LMS parameters: L2-H5-W8
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info: wc_LmsKey_Verify returned OK
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Successfully selected image in part: 0
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Firmware Valid
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Loading flash image from 8014A8 to RAM at 10000000 (226024 bytes)
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Loading elf at 10000000
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Found valid elf64 (little endian)
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Program Headers 2 (size 56)
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Load 57536 bytes (offset 10000) to 0 (p 0)
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Clear 20600 bytes at 0 (p 0)
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Entry point 0
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DTB boot partition: 7B0000
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Failed parsing DTB to load
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Booting at 0
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Hello World
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Successfully ran Hello World application
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```
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### Adding RSA Authentication
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1. Generate keys:
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* `bootgen.exe -generate_keys auth pem -arch zynqmp -image boot_auth.bif`
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2. Create hash for primary key:
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* `bootgen.exe -image boot_auth.bif -arch zynqmp -w -o i BOOT.BIN -efuseppkbits ppkf_hash.txt`
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3. Import example project for programming eFuses:
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* New BSP project (program efuses , ZCU102_hw_platform, standalone, CPU: PSU_cortexa53_0)
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* Goto Xilinx Board Support Packet Settings.
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* Scroll down to Supported Libraries and Check the xiskey library
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* In the system.mss pane, scroll down to Libraries and click Import Examples.
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* Check the xilskey_esfuseps_zynqmp_example
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4. Edit `xilskey_efuseps_zynqmp_input.h`
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* 433 `#define XSK_EFUSEPS_WRITE_PPK0_HASH TRUE`
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* 453 `#define XSK_EFUSEPS_PPK0_IS_SHA3 TRUE`
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* 454 `#define XSK_EFUSEPS_PPK0_HASH "0000000000000000000000000000000000000000000000000000000000000000" /* from ppkf_hash.txt */`
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5. Update boot.bif (see boot_auth.bif)
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```
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[auth_params] ppk_select=0; spk_id=0x00000000
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[pskfile] pskf.pem
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[sskfile] sskf.pem
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authentication=rsa
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```
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6. Build “boot.bin” image:
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* `bootgen -image boot_auth.bif -arch zynqmp -o i BOOT.BIN -w`
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Note: During testing add `[fsbl_config] bh_auth_enable` to allow skipping of the eFuse check of the PPK hash. In production the RSA_EN eFuses must be blown to force checking of the PPK hash.
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Note: To generate a report of a boot.bin use the `bootgen_utility` or after 2022.1 use `bootgen -read`:
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`bootgen -arch zynqmp -read BOOT.BIN`
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## CSU Support
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The Configuration Security Unit (CSU) is a dedicate core that contains security functions like PUF, SHA3, RSA, Tamper Protection. These registers can only be accessed through the PMU, which is a separate dedicated core. If operating from LE2 or lower the calls must be done through the BL31 (TF-A) SIP service to elevate privledges.
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Access to most CSU registers can be done by setting the `-DSECURE_ACCESS_VAL=1` build option.
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In PetaLinux menuconfig under PMU Configuration add compiler flag `-DSECURE_ACCESS_VAL=1`.
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```sh
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petalinux-build -c pmufw
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```
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### CSU PUF
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The PUF (Physically Unclonable Function) provides a way to generate a unique key for encryption specific to the device. It is useful for wrapping other keys to pair/bind them and allows external storage of the encrypted key.
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This feature is enabled with `CFLAGS_EXTRA+=-DCSU_PUF_ROT`.
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For PUF functionality a patch must be applied to the PMUFW to enable access to the PUF registers. See `pm_mmio_access.c` patch below:
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```
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+ /* CSU PUF Registers */
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+ {
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+ .startAddr = ( ( CSU_BASEADDR ) + 0X00004000 ),
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+ .endAddr = ( ( CSU_BASEADDR ) + 0X00004018 ),
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+ .access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK |
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+ IPI_PMU_0_IER_RPU_0_MASK |
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+ IPI_PMU_0_IER_RPU_1_MASK),
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+ },
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```
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Example PUF Generation Output:
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```
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wolfBoot Secure Boot
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Current EL: 2
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QSPI Init: Ref=300MHz, Div=8, Bus=37500000, IO=DMA
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Read FlashID Lower: Ret 0, 20 BB 22
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Read FlashID Upper: Ret 0, 20 BB 22
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PMUFW Ver: 1.1
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CSU ID 0x24738093, Ver 0x00000003
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PUF Status 0x00000002
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eFuse SEC_CTRL 0x00000000
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eFuse PUF CHASH 0x00000000, AUX 0x00000000
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CSU Puf Register
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Ret 0, Syndrome 1544, CHASH 0x9B7A8C30, AUX 0x005AE021
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4662F39BEC998700E2D299E15B30F1AF563FC596A3854ACE05FDA4FBC2AD32DF9B66E2081A55D8CA0CB84B88735B005548C0671BD561AE7A9FBB266E228368F6D1FD916C8D172572094E210826106B8C80AB1E8910647283DB22076560FC5E10C02C614F4EF80001B218501AD9D07580C2DB47E487940DB24615509EBE85B037AB2FCDE820661EAB45C345863735F64689AECCEAE783DC413052E615B231931E265EC00C15D8FCD2D83E9F8FC836178C0415587E683D48A7ADADC1B53E17743859CA5984A314D1CC85AF58226376E705AC6C2973ACCE05FF2263DBE951A2D0FFD9D218C57F1D1398640E5A3D03BB9478530035952642C40258AFEB196F0A6D130BC8C2E064C622AC9FA0827BBFCF35FCBAFC9593085D1D296F8446C3550784DECF964B4A65249E9A002A7CEE9886DBB7F33DC3A7404C66497218FF7762E4C81B048986BF9257968FF92D6F7D1AACB1A8CDE48E8ECDD8B7A74C3C16FF10FD00D119E3B5F4DB19854AF60C2B063CB26A3740FC8658425EB44F27B52CDD6C1A16E3C45394BA9629B0A8A0410979CA0ED488E787F36B4BC05E1CEBD8F5CFF6DAF3D3F8B885E6F0A616675DA0B748F3C4E334545920C3062113230741795AA97D4A32B7E1BC4953E588902C7915CD362B75DA33BB941B523932B172589E27759A924A857CD66EE0E02BE697188776E4A646F7A73203E769285BF9FD09562A67CC67E2EB6CC7D8F15C138991AC177030D9057750A70E0C4F6144A8412F436A8B952597D664BADF3997DC0249DB4ABF6355DEB09B7A8C300000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009B7A8C30005AE021
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CSU Register PUF 0: 281ms
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Regen: PUF Status 0x05AE0218
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CSU Regen PUF 0: 8ms
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Red Key 32
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64F03AFD7D0C70D2591CDF34305F7B8A5BA4593C0A0E1B8C5ECDFF9F5900192C
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Black IV 16
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D142AC7C560F158BA95A213100000000
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Black Key 32
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2599B8619240E98E264A0CE3CD42C58A9E3457F1982D1DEEE1FC75A1A1284C72
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```
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Example .bif that includes the PUF helper data and black key/iv. This enables the CSU boot ROM to load up the black AES key for use with the CSU AES engine.
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```
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the_ROM_image:
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{
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// Boot Header Authentication Enable
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[fsbl_config] a53_x64, bh_auth_enable, puf4kmode, shutter=0x0100005E, pufhd_bh
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[keysrc_encryption] bh_blk_key
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[puf_file] helperdata.txt
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[bh_key_iv] black_iv.txt
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[bh_keyfile] black_key.txt
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// Use the primary public key 0 and secondary public key id 0
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[auth_params] ppk_select=0; spk_id=0x00000000
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// primary and secondary secret (private) keys
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[pskfile] pskf.pem
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[sskfile] sskf.pem
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[bootloader, authentication=rsa, encryption=aes, destination_cpu=a53-0] zynqmp_fsbl.elf
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[destination_cpu=pmu, authentication=rsa] pmufw.elf
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[destination_device=pl, authentication=rsa] system.bit
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[destination_cpu=a53-0, authentication=rsa, exception_level=el-3, trustzone] bl31.elf
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[destination_cpu=a53-0, authentication=rsa, load=0x00100000] system.dtb
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[destination_cpu=a53-0, authentication=rsa, exception_level=el-2] wolfboot.elf
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[destination_cpu=a53-0, partition_owner=uboot, offset=0x800000] hello_world_v1_signed.bin
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}
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```
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Generated BOOT.BIN using: `bootgen -image bootgen.bif -arch zynqmp -o BOOT.BIN -w -p xzcu9eg`
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This will create an encryption key file `zynqmp_fsbl.nky`.
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### CSU JTAG Enable
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When RSA authentication is enabled the JTAG feature is disabled in the PMU. To re-enable it (assuming eFuse allows it) build with `CFLAGS_EXTRA+=-DDEBUG_CSU=2` and apply the PMUFW patches below.
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To patch the PMUFW from PetaLinux use the following steps (for 2022.1 or later):
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Based on instructions from: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/2587197506/Zynq+UltraScale+MPSoC+JTAG+Enable+in+U-Boot
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`pim/project-spec/meta-user/recipes-bsp/embeddedsw/pmu-firmware_%.bbappend`:
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```
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# Patch for PMUFW
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SRC_URI_append = " file://0001-csu-regs.patch"
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FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
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```
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`pim/project-spec/meta-user/recipes-bsp/embeddedsw/files/0001-csu-regs.patch`:
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```
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diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_mmio_access.c b/lib/sw_apps/zynqmp_pmufw/src/pm_mmio_access.c
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index 73066576a5..ce9490916d 100644
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--- a/lib/sw_apps/zynqmp_pmufw/src/pm_mmio_access.c
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+++ b/lib/sw_apps/zynqmp_pmufw/src/pm_mmio_access.c
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@@ -99,6 +99,22 @@ static const PmAccessRegion pmAccessTable[] = {
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IPI_PMU_0_IER_RPU_1_MASK),
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},
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+ /* WOLF: Adding DBG_LPD_CTRL and RST_LPD_DBG to support JTAG Enable in u-boot */
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+ {
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+ .startAddr = CRL_APB_DBG_LPD_CTRL,
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+ .endAddr = CRL_APB_DBG_LPD_CTRL,
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+ .access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK |
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+ IPI_PMU_0_IER_RPU_0_MASK |
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+ IPI_PMU_0_IER_RPU_1_MASK),
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+ },
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+ {
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+ .startAddr = CRL_APB_RST_LPD_DBG,
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+ .endAddr = CRL_APB_RST_LPD_DBG,
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+ .access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK |
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+ IPI_PMU_0_IER_RPU_0_MASK |
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+ IPI_PMU_0_IER_RPU_1_MASK),
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+ },
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+
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/* PMU's global Power Status register*/
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{
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.startAddr = PMU_GLOBAL_PWR_STATE,
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@@ -415,15 +431,24 @@ static const PmAccessRegion pmAccessTable[] = {
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IPI_PMU_0_IER_RPU_1_MASK),
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},
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+ /* WOLF: separate CSU_JTAG_CHAIN_CFG so it can be made RW */
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/* CSU ier register*/
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{
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.startAddr = CSU_IER,
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- .endAddr = CSU_JTAG_CHAIN_CFG,
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+ .endAddr = CSU_IDR,
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.access = MMIO_ACCESS_WO(IPI_PMU_0_IER_APU_MASK |
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IPI_PMU_0_IER_RPU_0_MASK |
|
|
IPI_PMU_0_IER_RPU_1_MASK),
|
|
},
|
|
|
|
+ {
|
|
+ .startAddr = CSU_JTAG_CHAIN_CFG,
|
|
+ .endAddr = CSU_JTAG_CHAIN_CFG,
|
|
+ .access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK |
|
|
+ IPI_PMU_0_IER_RPU_0_MASK |
|
|
+ IPI_PMU_0_IER_RPU_1_MASK),
|
|
+ },
|
|
+
|
|
/* CSU idr register*/
|
|
{
|
|
.startAddr = CSU_IDR,
|
|
@@ -504,6 +529,15 @@ static const PmAccessRegion pmAccessTable[] = {
|
|
IPI_PMU_0_IER_RPU_1_MASK),
|
|
},
|
|
|
|
+ /* CSU PUF Registers */
|
|
+ {
|
|
+ .startAddr = ( ( CSU_BASEADDR ) + 0X00004000 ),
|
|
+ .endAddr = ( ( CSU_BASEADDR ) + 0X00004018 ),
|
|
+ .access = MMIO_ACCESS_RW(IPI_PMU_0_IER_APU_MASK |
|
|
+ IPI_PMU_0_IER_RPU_0_MASK |
|
|
+ IPI_PMU_0_IER_RPU_1_MASK),
|
|
+ },
|
|
+
|
|
/*CSU tamper-status register */
|
|
{
|
|
.startAddr = CSU_TAMPER_STATUS,
|
|
```
|
|
|
|
Then rebuild PMUFW: `petalinux-build -c pmufw`
|
|
|
|
|
|
## Post Quantum
|
|
|
|
### PQ XMSS
|
|
|
|
1) Add these build symbols to the Xilinx project:
|
|
Note: Make sure and remove the existing `WOLFBOOT_SIGN_*`, `WOLFBOOT_HASH_*` and `IMAGE_HEADER_SIZE`
|
|
|
|
```
|
|
WOLFBOOT_SIGN_XMSS
|
|
WOLFBOOT_HASH_SHA256
|
|
WOLFSSL_HAVE_XMSS
|
|
WOLFSSL_WC_XMSS
|
|
WOLFSSL_WC_XMSS_SMALL
|
|
WOLFBOOT_XMSS_PARAMS='\"XMSS-SHA2_10_256\"'
|
|
WOLFSSL_XMSS_VERIFY_ONLY
|
|
WOLFSSL_XMSS_MAX_HEIGHT=32
|
|
WOLFBOOT_SHA_BLOCK_SIZE=4096
|
|
IMAGE_SIGNATURE_SIZE=2500
|
|
XMSS_IMAGE_SIGNATURE_SIZE=2500
|
|
IMAGE_HEADER_SIZE=5000
|
|
```
|
|
|
|
2) Create and sign image:
|
|
|
|
```sh
|
|
$ ./tools/keytools/keygen --xmss -g wolfboot_signing_private_key.der
|
|
Keytype: XMSS
|
|
Generating key (type: XMSS)
|
|
info: using XMSS parameters: XMSS-SHA2_10_256
|
|
Associated key file: wolfboot_signing_private_key.der
|
|
Partition ids mask: ffffffff
|
|
Key type : XMSS
|
|
Public key slot: 0
|
|
Done.
|
|
|
|
$ ./tools/keytools/sign --xmss ../hello_world/Debug/hello_world.elf wolfboot_signing_private_key.der 1
|
|
wolfBoot KeyTools (Compiled C version)
|
|
wolfBoot version 2020000
|
|
Update type: Firmware
|
|
Input image: ../hello_world/Debug/hello_world.elf
|
|
Selected cipher: XMSS
|
|
Selected hash : SHA256
|
|
Public key: wolfboot_signing_private_key.der
|
|
Output image: ../hello_world/Debug/hello_world_v1_signed.bin
|
|
Target partition id : 1
|
|
info: using XMSS parameters: XMSS-SHA2_10_256
|
|
info: XMSS signature size: 2500
|
|
info: xmss sk len: 1343
|
|
info: xmss pk len: 68
|
|
Found XMSS key
|
|
image header size calculated at runtime (5000 bytes)
|
|
Calculating SHA256 digest...
|
|
Signing the digest...
|
|
Output image(s) successfully created.
|
|
```
|
|
|
|
### PQ LMS
|
|
|
|
1) Add these build symbols to the Xilinx project:
|
|
Note: Make sure and remove the existing `WOLFBOOT_SIGN_*`, `WOLFBOOT_HASH_*` and `IMAGE_HEADER_SIZE`
|
|
|
|
```
|
|
WOLFBOOT_SIGN_LMS
|
|
WOLFBOOT_HASH_SHA256
|
|
WOLFSSL_HAVE_LMS
|
|
WOLFSSL_WC_LMS
|
|
WOLFSSL_WC_LMS_SMALL
|
|
WOLFSSL_LMS_VERIFY_ONLY
|
|
WOLFSSL_LMS_MAX_LEVELS=2
|
|
WOLFSSL_LMS_MAX_HEIGHT=5
|
|
LMS_LEVELS=2
|
|
LMS_HEIGHT=5
|
|
LMS_WINTERNITZ=8
|
|
IMAGE_SIGNATURE_SIZE=2644
|
|
IMAGE_HEADER_SIZE=5288
|
|
```
|
|
2) Create and sign image:
|
|
|
|
```sh
|
|
$ ./tools/keytools/keygen --lms -g wolfboot_signing_private_key.der
|
|
Keytype: LMS
|
|
Generating key (type: LMS)
|
|
info: using LMS parameters: L2-H5-W8
|
|
Associated key file: wolfboot_signing_private_key.der
|
|
Partition ids mask: ffffffff
|
|
Key type : LMS
|
|
Public key slot: 0
|
|
Done.
|
|
|
|
$ ./tools/keytools/sign --lms ../hello_world/Debug/hello_world.elf wolfboot_signing_private_key.der 1
|
|
wolfBoot KeyTools (Compiled C version)
|
|
wolfBoot version 2020000
|
|
Update type: Firmware
|
|
Input image: ../hello_world/Debug/hello_world.elf
|
|
Selected cipher: LMS
|
|
Selected hash : SHA256
|
|
Public key: wolfboot_signing_private_key.der
|
|
Output image: ../hello_world/Debug/hello_world_v1_signed.bin
|
|
Target partition id : 1
|
|
info: using LMS parameters: L2-H5-W8
|
|
info: LMS signature size: 2644
|
|
Found LMS key
|
|
image header size calculated at runtime (5288 bytes)
|
|
Calculating SHA256 digest...
|
|
Signing the digest...
|
|
Output image(s) successfully created.
|
|
```
|
|
|
|
|
|
### References:
|
|
* [ZAPP1319](https://www.xilinx.com/support/documentation/application_notes/xapp1319-zynq-usp-prog-nvm.pdf): Programming BBRAM and eFUSEs
|
|
* [UG1283](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug1283-bootgen-user-guide.pdf): Bootgen User Guide
|
|
* [Using Cryptography in Zynq UltraScale MPSoC](https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842541/Using+Cryptography+in+Zynq+UltraScale+MPSoC)
|