mirror of https://github.com/wolfSSL/wolfBoot.git
521 lines
24 KiB
C
521 lines
24 KiB
C
/* spi_drv_stm32.h
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#ifndef SPI_DRV_STM32_H_INCLUDED
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#define SPI_DRV_STM32_H_INCLUDED
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#include <stdint.h>
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#ifdef PLATFORM_stm32f4
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#define APB2_CLOCK_ER (*(volatile uint32_t *)(0x40023844))
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#define APB2_CLOCK_RST (*(volatile uint32_t *)(0x40023824))
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#define RCC_GPIO_CLOCK_ER (*(volatile uint32_t *)(0x40023830))
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#define GPIOA_BASE (0x40020000)
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#define GPIOB_BASE (0x40020400)
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#define GPIOC_BASE (0x40020800)
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#define GPIOD_BASE (0x40020C00)
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#define GPIOE_BASE (0x40021000)
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#define GPIO_BASE GPIOA_BASE
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#define SPI_GPIO GPIOB_BASE
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#define SPI_CS_GPIO GPIOE_BASE
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#define SPI_CS_FLASH 1 /* Flash CS connected to GPIOE1 */
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#define SPI_CS_TPM 0 /* TPM CS connected to GPIOE0 */
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#define SPI_PIN_AF 5 /* Alternate function for SPI pins */
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#define SPI_CLOCK_PIN 3 /* SPI_SCK: PB3 */
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#define SPI_MISO_PIN 4 /* SPI_MISO PB4 */
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#define SPI_MOSI_PIN 5 /* SPI_MOSI PB5 */
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#endif /* PLATFORM_stm32f4 */
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#ifdef PLATFORM_stm32u5
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#ifdef TZEN
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#define PERIPH_BASE (0x50000000UL)
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#else
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#define PERIPH_BASE (0x40000000UL)
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#endif
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#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
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#define AHB2PERIPH_BASE (PERIPH_BASE + 0x02020000UL)
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#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
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#define RCC_BASE (APB2PERIPH_BASE + 0x0C00UL)
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#define APB2_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0xA4))
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#define APB2_CLOCK_RST (*(volatile uint32_t *)(RCC_BASE + 0x7C))
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#define RCC_GPIO_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0x8C))
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#define GPIO_BASE (APB2PERIPH_BASE + 0x02020000UL)
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#define GPIOA_BASE (GPIO_BASE + 0x00000UL)
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#define GPIOB_BASE (GPIO_BASE + 0x00400UL)
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#define GPIOC_BASE (GPIO_BASE + 0x00800UL)
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#define GPIOD_BASE (GPIO_BASE + 0x00C00UL)
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#define GPIOE_BASE (GPIO_BASE + 0x01000UL)
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#define GPIOF_BASE (GPIO_BASE + 0x01400UL)
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#define GPIOG_BASE (GPIO_BASE + 0x01800UL)
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#define GPIOH_BASE (GPIO_BASE + 0x01C00UL)
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#define GPIOI_BASE (GPIO_BASE + 0x02000UL)
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/* STMOD+ Port */
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#define SPI_GPIO GPIOE_BASE
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#define SPI_CS_GPIO GPIOE_BASE
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#define SPI_CS_FLASH 11 /* Flash CS connected to GPIOE11 */
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#define SPI_CS_TPM 10 /* TPM CS connected to GPIOE10 */
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#define SPI_PIN_AF 5 /* Alternate function for SPI pins */
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#define SPI_CLOCK_PIN 13 /* SPI_SCK: PE13 */
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#define SPI_MISO_PIN 14 /* SPI_MISO PE14 */
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#define SPI_MOSI_PIN 15 /* SPI_MOSI PE15 */
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#endif /* PLATFORM_stm32u5 */
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#ifdef PLATFORM_stm32wb
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#define APB2_CLOCK_ER (*(volatile uint32_t *)(0x58000060))
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#define APB2_CLOCK_RST (*(volatile uint32_t *)(0x58000040))
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#define RCC_GPIO_CLOCK_ER (*(volatile uint32_t *)(0x5800004C))
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#define GPIOA_BASE (0x48000000)
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#define GPIOB_BASE (0x48000400)
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#define GPIOC_BASE (0x48000800)
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#define GPIOD_BASE (0x48000C00)
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/* STM32WB55 NUCLEO: CN9: D13=SCK, D12=MISO, D11=MOSI, FLASHCS=D10, TPMCS=D9 */
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#define SPI_GPIO GPIOA_BASE
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#define SPI_CS_GPIO GPIOA_BASE
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#define SPI_CS_FLASH 4 /* Flash CS connected to GPIOA4 */
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#define SPI_CS_TPM 9 /* TPM CS connected to GPIOA9 */
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#define SPI_PIN_AF 5 /* Alternate function for SPI pins */
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#define SPI_CLOCK_PIN 5 /* SPI_SCK: PA5 */
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#define SPI_MISO_PIN 6 /* SPI_MISO PA6 */
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#define SPI_MOSI_PIN 7 /* SPI_MOSI PA7 */
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#endif /* PLATFORM_stm32wb */
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#ifdef PLATFORM_stm32l0
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#define APB2_CLOCK_ER (*(volatile uint32_t *)(0x40021034))
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#define APB2_CLOCK_RST (*(volatile uint32_t *)(0x40021024))
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#define RCC_GPIO_CLOCK_ER (*(volatile uint32_t *)(0x4002102C))
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#define GPIOA_BASE (0x50000000)
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#define GPIOB_BASE (0x50000400)
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#define SPI_CS_GPIO GPIOB_BASE
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#define SPI_PIN_AF 0 /* Alternate function for SPI pins */
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#ifndef SPI_ALT_CONFIGURATION
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#define SPI_GPIO GPIOB_BASE
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#define SPI_CS_FLASH 8 /* Flash CS connected to GPIOB8 */
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#define SPI_CLOCK_PIN 3 /* SPI_SCK: PB3 */
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#define SPI_MISO_PIN 4 /* SPI_MISO PB4 */
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#define SPI_MOSI_PIN 5 /* SPI_MOSI PB5 */
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#else
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#define SPI_GPIO GPIOA_BASE
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#define SPI_CS_FLASH 6 /* Flash CS connected to GPIOB6 */
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#define SPI_CLOCK_PIN 5 /* SPI_SCK: PA5 */
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#define SPI_MISO_PIN 6 /* SPI_MISO PA6 */
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#define SPI_MOSI_PIN 7 /* SPI_MOSI PA7 */
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#endif /* SPI_ALT_CONFIGURATION */
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#endif /* PLATFORM_stm32l0 */
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#ifdef PLATFORM_stm32h7
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#define RCC_BASE (0x58024400UL)
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#define RCC_GPIO_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0xE0)) /* RM0433 - 8.7.43 (RCC_AHB4ENR) */
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#define APB2_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0xF0)) /* RM0433 - 8.7.47 */
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#define APB2_CLOCK_RST (*(volatile uint32_t *)(RCC_BASE + 0x98)) /* RM0433 - 8.7.35 */
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#define DLYB_QSPI_BASE (0x52006000UL)
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#define DLYB_CR(base) (*(volatile uint32_t *)((base) + 0x00)) /* Control register */
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#define DLYB_CFGR(base) (*(volatile uint32_t *)((base) + 0x04)) /* Configuration register */
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#define DLYB_CR_SEN (1 << 1) /* Sampler length enable bit */
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#define DLYB_CR_DEN (1 << 0) /* Delay block enable bit */
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#define GPIOA_BASE (0x58020000)
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#define GPIOB_BASE (0x58020400)
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#define GPIOC_BASE (0x58020800)
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#define GPIOD_BASE (0x58020C00)
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#define GPIOE_BASE (0x58021000)
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#define GPIOF_BASE (0x58021400)
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#define GPIOG_BASE (0x58021800)
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#define GPIOH_BASE (0x58021C00)
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#define GPIOI_BASE (0x58022000)
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#define GPIOJ_BASE (0x58022400)
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#define GPIOK_BASE (0x58022800)
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/** QSPI **/
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/* Default Base (E) and AF (alternate function=10) for QSPI */
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#define QSPI_GPIO GPIOE_BASE
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#define QSPI_PIN_AF 10
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/* Default to flash bank 1 (2 for alt) */
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#ifndef QSPI_FLASH_BANK
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#ifdef QSPI_ALT_CONFIGURATION
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#define QSPI_FLASH_BANK 2
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#else
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#define QSPI_FLASH_BANK 1
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#endif
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#endif
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/* Default flash size to 16MB */
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#ifndef QSPI_FLASH_SIZE
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#define QSPI_FLASH_SIZE 23 /* 2^24 = 16 MB */
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#endif
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/* QSPI uses hclk3 (240MHz max) by default */
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#define RCC_D1CCIPR (*(volatile uint32_t *)(RCC_BASE + 0x4C)) /* RM0433 - 8.7.19 (RCC_D1CCIPR) */
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#define RCC_D1CCIPR_QSPISEL_MASK (0x3 << 4)
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#define RCC_D1CCIPR_QSPISEL(sel) (((sel) & 0x3) << 4) /* 0=hclk3, 1=pll1_q_ck, 2=pll2_r_ck, 3=per_ck */
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#define RCC_D1CCIPR_QSPISEL_HCLK3 0
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#define RCC_D1CCIPR_QSPISEL_PLL1 1
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#define RCC_D1CCIPR_QSPISEL_PLL2 2
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#define RCC_D1CCIPR_QSPISEL_PERCK 3
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#define AHB3_CLOCK_RST (*(volatile uint32_t *)(RCC_BASE + 0x7C)) /* RM0433 - 8.7.28 - RCC_AHB3RSTR */
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#define AHB3_CLOCK_EN (*(volatile uint32_t *)(RCC_BASE + 0xD4)) /* RM0433 - 8.7.40 - RCC_AHB3ENR */
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#define RCC_AHB3ENR_QSPIEN (1 << 14) /* QUADSPI/OCTOSPI clock enabled */
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#define HCLK3_MHZ 240000000
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#define PERCK_MHZ 64000000
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#ifndef QSPI_CLOCK_BASE
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#define QSPI_CLOCK_BASE PERCK_MHZ
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#endif
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#ifndef QSPI_CLOCK_SEL
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/* Enable QUADSPI clock on PER_CK (64MHz) */
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#define QSPI_CLOCK_SEL RCC_D1CCIPR_QSPISEL_PERCK
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#endif
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#ifndef QSPI_CLOCK_MHZ
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#define QSPI_CLOCK_MHZ 16000000
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#endif
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/* QSPI CLK PB2 (alt OCTOSPIM_P1_CLK)*/
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#define QSPI_CLOCK_PIO_BASE GPIOB_BASE
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#define QSPI_CLOCK_PIN 2
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#define QSPI_CLOCK_PIN_AF 9
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/* nQSPI_CS PG6 (alt PB6 -> OCTOSPIM_P1_NCS) */
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#ifndef QSPI_ALT_CONFIGURATION
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#define QSPI_CS_PIO_BASE GPIOG_BASE
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#define QSPI_CS_FLASH_PIN 6
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#else
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#define QSPI_CS_PIO_BASE GPIOB_BASE
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#define QSPI_CS_FLASH_PIN 6
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#endif
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/* QSPI_IO0 (MOSI) - PD11 (alt PE7 -> OCTOSPIM_P1_IO4) */
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#ifndef QSPI_ALT_CONFIGURATION
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#define QSPI_IO0_PIO_BASE GPIOD_BASE
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#define QSPI_IO0_PIN 11
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#define QSPI_IO0_PIN_AF 9
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#else
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#define QSPI_IO0_PIO_BASE GPIOE_BASE
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#define QSPI_IO0_PIN 7
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#endif
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/* QSPI_IO1 (MISO) - PD12 (alt PE8 -> OCTOSPIM_P1_IO5) */
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#ifndef QSPI_ALT_CONFIGURATION
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#define QSPI_IO1_PIO_BASE GPIOD_BASE
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#define QSPI_IO1_PIN 12
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#define QSPI_IO1_PIN_AF 9
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#else
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#define QSPI_IO1_PIO_BASE GPIOE_BASE
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#define QSPI_IO1_PIN 8
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#endif
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/* QSPI_IO2 - PE2 (alt PE9 -> OCTOSPIM_P1_IO6) */
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#ifndef QSPI_ALT_CONFIGURATION
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#define QSPI_IO2_PIO_BASE GPIOE_BASE
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#define QSPI_IO2_PIN 2
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#define QSPI_IO2_PIN_AF 9
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#else
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#define QSPI_IO2_PIO_BASE GPIOE_BASE
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#define QSPI_IO2_PIN 9
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#endif
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/* QSPI_IO3 - PD13 (alt PE10 -> OCTOSPIM_P1_IO7) */
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#ifndef QSPI_ALT_CONFIGURATION
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#define QSPI_IO3_PIO_BASE GPIOD_BASE
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#define QSPI_IO3_PIN 13
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#define QSPI_IO3_PIN_AF 9
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#else
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#define QSPI_IO3_PIO_BASE GPIOE_BASE
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#define QSPI_IO3_PIN 10
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#endif
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#endif /* PLATFORM_stm32h7 */
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/* Setup SPI PIO Bases */
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#ifndef SPI_CLOCK_PIO_BASE
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#define SPI_CLOCK_PIO_BASE SPI_GPIO
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#endif
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#ifndef SPI_MISO_PIO_BASE
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#define SPI_MISO_PIO_BASE SPI_GPIO
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#endif
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#ifndef SPI_MOSI_PIO_BASE
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#define SPI_MOSI_PIO_BASE SPI_GPIO
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#endif
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#ifndef SPI_CS_PIO_BASE
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#define SPI_CS_PIO_BASE SPI_CS_GPIO
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#endif
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#ifndef SPI_CS_TPM_PIO_BASE
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#define SPI_CS_TPM_PIO_BASE SPI_CS_GPIO
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#endif
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#if defined(QSPI_FLASH) || defined(OCTOSPI_FLASH)
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#ifndef QSPI_CS_PIO_BASE
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#define QSPI_CS_PIO_BASE QSPI_CS_GPIO
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#endif
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#ifndef QSPI_CLOCK_PIO_BASE
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#define QSPI_CLOCK_PIO_BASE QSPI_GPIO
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#endif
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#ifndef QSPI_IO0_PIO_BASE
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#define QSPI_IO0_PIO_BASE QSPI_GPIO
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#endif
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#ifndef QSPI_IO1_PIO_BASE
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#define QSPI_IO1_PIO_BASE QSPI_GPIO
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#endif
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#ifndef QSPI_IO2_PIO_BASE
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#define QSPI_IO2_PIO_BASE QSPI_GPIO
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#endif
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#ifndef QSPI_IO3_PIO_BASE
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#define QSPI_IO3_PIO_BASE QSPI_GPIO
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#endif
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#endif /* QSPI_FLASH || OCTOSPI_FLASH */
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/* Setup alternate functions */
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#ifndef SPI_CLOCK_PIN_AF
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#define SPI_CLOCK_PIN_AF SPI_PIN_AF
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#endif
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#ifndef SPI_MISO_PIN_AF
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#define SPI_MISO_PIN_AF SPI_PIN_AF
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#endif
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#ifndef SPI_MOSI_PIN_AF
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#define SPI_MOSI_PIN_AF SPI_PIN_AF
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#endif
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#if defined(QSPI_FLASH) || defined(OCTOSPI_FLASH)
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#ifndef QSPI_CS_FLASH_AF
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#define QSPI_CS_FLASH_AF QSPI_PIN_AF
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#endif
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#ifndef QSPI_CLOCK_PIN_AF
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#define QSPI_CLOCK_PIN_AF QSPI_PIN_AF
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#endif
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#ifndef QSPI_IO0_PIN_AF
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#define QSPI_IO0_PIN_AF QSPI_PIN_AF
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#endif
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#ifndef QSPI_IO1_PIN_AF
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#define QSPI_IO1_PIN_AF QSPI_PIN_AF
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#endif
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#ifndef QSPI_IO2_PIN_AF
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#define QSPI_IO2_PIN_AF QSPI_PIN_AF
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#endif
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#ifndef QSPI_IO3_PIN_AF
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#define QSPI_IO3_PIN_AF QSPI_PIN_AF
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#endif
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#endif /* QSPI_FLASH || OCTOSPI_FLASH */
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/* SPI */
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#ifndef SPI1_BASE
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#define SPI1_BASE (0x40013000) /* SPI1 base address */
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#endif
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#define SPI1_APB2_CLOCK_ER_VAL (1 << 12)
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#define SPI1_CR1 (*(volatile uint32_t *)(SPI1_BASE))
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#define SPI1_CR2 (*(volatile uint32_t *)(SPI1_BASE + 0x04))
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#define SPI1_SR (*(volatile uint32_t *)(SPI1_BASE + 0x08))
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#define SPI1_DR (*(volatile uint32_t *)(SPI1_BASE + 0x0c))
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#define SPI_CR1_CLOCK_PHASE (1 << 0)
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#define SPI_CR1_CLOCK_POLARITY (1 << 1)
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#define SPI_CR1_MASTER (1 << 2)
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#define SPI_CR1_BAUDRATE (0x07 << 3)
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#define SPI_CR1_SPI_EN (1 << 6)
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#define SPI_CR1_LSBFIRST (1 << 7)
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#define SPI_CR1_SSI (1 << 8)
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#define SPI_CR1_SSM (1 << 9)
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#define SPI_CR1_16BIT_FORMAT (1 << 11)
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#define SPI_CR1_TX_CRC_NEXT (1 << 12)
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#define SPI_CR1_HW_CRC_EN (1 << 13)
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#define SPI_CR1_BIDIOE (1 << 14)
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#define SPI_CR2_SSOE (1 << 2)
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#define SPI_SR_RX_NOTEMPTY (1 << 0)
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#define SPI_SR_TX_EMPTY (1 << 1)
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#define SPI_SR_BUSY (1 << 7)
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/* GPIO */
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#define GPIO_MODE(base) (*(volatile uint32_t *)(base + 0x00)) /* GPIOx_MODER */
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#define GPIO_OTYPE(base) (*(volatile uint32_t *)(base + 0x04)) /* GPIOx_OTYPER */
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#define GPIO_OSPD(base) (*(volatile uint32_t *)(base + 0x08)) /* GPIOx_OSPEEDR */
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#define GPIO_PUPD(base) (*(volatile uint32_t *)(base + 0x0c)) /* GPIOx_PUPDR */
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#define GPIO_ODR(base) (*(volatile uint32_t *)(base + 0x14)) /* GPIOx_ODR */
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#define GPIO_BSRR(base) (*(volatile uint32_t *)(base + 0x18)) /* GPIOx_BSRR */
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#define GPIO_AFL(base) (*(volatile uint32_t *)(base + 0x20)) /* GPIOx_AFRL */
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#define GPIO_AFH(base) (*(volatile uint32_t *)(base + 0x24)) /* GPIOx_AFRH */
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#define GPIO_MODE_INPUT (0)
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#define GPIO_MODE_OUTPUT (1)
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#define GPIO_MODE_AF (2)
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#define GPIO_MODE_ANALOG (3)
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/* QUADSPI */
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#ifndef QUADSPI_BASE
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#define QUADSPI_BASE 0x52005000UL
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#endif
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#define QUADSPI_CR (*(volatile uint32_t *)(QUADSPI_BASE + 0x00)) /* Control register */
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#define QUADSPI_DCR (*(volatile uint32_t *)(QUADSPI_BASE + 0x04)) /* Device Configuration register */
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#define QUADSPI_SR (*(volatile uint32_t *)(QUADSPI_BASE + 0x08)) /* Status register */
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#define QUADSPI_FCR (*(volatile uint32_t *)(QUADSPI_BASE + 0x0C)) /* Flag Clear register */
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#define QUADSPI_DLR (*(volatile uint32_t *)(QUADSPI_BASE + 0x10)) /* Data Length register */
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#define QUADSPI_CCR (*(volatile uint32_t *)(QUADSPI_BASE + 0x14)) /* Communication Configuration register */
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#define QUADSPI_AR (*(volatile uint32_t *)(QUADSPI_BASE + 0x18)) /* Address register */
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#define QUADSPI_ABR (*(volatile uint32_t *)(QUADSPI_BASE + 0x1C)) /* Alternate Bytes register */
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#define QUADSPI_DR (*(volatile uint8_t *)(QUADSPI_BASE + 0x20)) /* Data register */
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#define QUADSPI_DR32 (*(volatile uint32_t *)(QUADSPI_BASE + 0x20)) /* Data register - 32 bit */
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#define QUADSPI_PSMKR (*(volatile uint32_t *)(QUADSPI_BASE + 0x24)) /* Polling Status Mask register */
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#define QUADSPI_PSMAR (*(volatile uint32_t *)(QUADSPI_BASE + 0x28)) /* Polling Status Match register */
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#define QUADSPI_PIR (*(volatile uint32_t *)(QUADSPI_BASE + 0x2C)) /* Polling Interval register */
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#define QUADSPI_LPTR (*(volatile uint32_t *)(QUADSPI_BASE + 0x30)) /* Low Power Timeout register */
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#define QUADSPI_CR_PRESCALER_MASK (0xFF << 24)
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#define QUADSPI_CR_PRESCALER(pre) ((((pre)-1) & 0xFF) << 24) /* Clock prescaler: quadspi_ker_ck/pre+1 */
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#define QUADSPI_CR_FTIE (1 << 13) /* FIFO threshold interrupt enable */
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#define QUADSPI_CR_FTHRES_MASK (0x1F << 8)
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#define QUADSPI_CR_FTHRES(thr) ((((thr)-1) & 0x1F) << 8) /* FIFO threshold level */
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#define QUADSPI_CR_FSEL (1 << 7) /* 0=Flash 1 or 1=Flash 2 */
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#define QUADSPI_CR_DFM (1 << 6) /* Dual-flash mode */
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#define QUADSPI_CR_SSHIFT (1 << 4) /* Sample shift 1=1/2 cycle shift */
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#define QUADSPI_CR_ABORT (1 << 1) /* Abort request */
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#define QUADSPI_CR_EN (1 << 0) /* Enable the QUADSPI */
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#define QUADSPI_CCR_DDRM (1 << 31) /* Double data rate mode */
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#define QUADSPI_CCR_DHHC (1 << 30) /* Delay the data output by 1/4 of the QUADSPI output clock cycle in DDR mode */
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#define QUADSPI_CCR_FRCM (1 << 29) /* Free running clock mode */
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#define QUADSPI_CCR_SIOO (1 << 28) /* Send instruction only once mode */
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#define QUADSPI_CCR_FMODE_MASK (0x3 << 26)
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#define QUADSPI_CCR_FMODE(fmode) (((fmode) & 0x3) << 26) /* Functional Mode (0=indirect write, 1=indirect read, 2=auto poll, 3=mem mapped) */
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#define QUADSPI_CCR_DMODE_MASK (0x3 << 24)
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#define QUADSPI_CCR_DMODE(dmode) (((dmode) & 0x3) << 24) /* Data mode (0=no data, 1=data on single line, 2=data on two lines, 3=data on four lines) */
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#define QUADSPI_CCR_DCYC_MASK (0x1F << 18)
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#define QUADSPI_CCR_DCYC(dcyc) (((dcyc) & 0x1F) << 18) /* Number of dummy cycles */
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#define QUADSPI_CCR_ABSIZE_MASK (0x3 << 16)
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#define QUADSPI_CCR_ABSIZE(absz) (((absz) & 0x3) << 16) /* Alternate bytes size */
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#define QUADSPI_CCR_ABMODE_MASK (0x3 << 14)
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#define QUADSPI_CCR_ABMODE(abmode) (((abmode) & 0x3) << 14) /* Alternate bytes mode (0=no alt data, 1=alt on single line, 2=alt on two lines, 3=alt on four lines) */
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#define QUADSPI_CCR_ADSIZE_MASK (0x3 << 12)
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#define QUADSPI_CCR_ADSIZE(sz) (((sz) & 0x3) << 12) /* Address bytes size (0=8-bit, 1=16-bit, 2=24-bit, 3=32-bit) */
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#define QUADSPI_CCR_ADMODE_MASK (0x3 << 10)
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#define QUADSPI_CCR_ADMODE(admode) (((admode) & 0x3) << 10) /* Address mode (0=no addr, 1=addr on single line, 2=addr on two lines, 3=addr on four lines) */
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#define QUADSPI_CCR_IMODE_MASK (0x3 << 8)
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#define QUADSPI_CCR_IMODE(imode) (((imode) & 0x3) << 8) /* Instruction mode (0=no instr, 1=instr on single line, 2=instr on two lines, 3=instr on four lines) */
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#define QUADSPI_CCR_INSTRUCTION_MASK (0xFF << 0)
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#define QUADSPI_CCR_INSTRUCTION(ins) (((ins) & 0xFF) << 0) /* Instruction to be send to the external SPI device */
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#define QUADSPI_DCR_FSIZE_MASK (0x1F << 16)
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#define QUADSPI_DCR_FSIZE(fsz) (((fsz) & 0x1F) << 16) /* Flash memory size (2 ^ (fsize + 1)). Example 16MB is 23 */
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#define QUADSPI_DCR_CSHT_MASK (0x7 << 8)
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#define QUADSPI_DCR_CSHT(csht) (((csht) & 0x7) << 8) /* Chip select high time - Number of clock cycles (+1) nCS to remain high between commands */
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#define QUADSPI_DCR_CKMODE_3 (1 << 0) /* Clock mode 3 - clk high while nCS released */
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#define QUADSPI_DCR_CKMODE_0 (0) /* Clock mode 0 - clk low while nCS released */
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#define QUADSPI_SR_TCF (1 << 1) /* Transfer complete flag - set in indirect mode when the programmed number of data has been transferred */
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#define QUADSPI_SR_FTF (1 << 2) /* FIFO threshold flag */
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#define QUADSPI_SR_BUSY (1 << 5) /* Busy - operation is ongoing when set */
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/* OCTOSPI (1=0x5000, 2=0xA000)*/
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#ifndef OCTOSPI_BASE
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#define OCTOSPI_BASE 0x52005000
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#endif
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#define OCTOSPI_CR (*(volatile uint32_t *)(OCTOSPI_BASE + 0x00)) /* Control register */
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#define OCTOSPI_DCR1 (*(volatile uint32_t *)(OCTOSPI_BASE + 0x08)) /* Device Configuration register 1 */
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#define OCTOSPI_DCR2 (*(volatile uint32_t *)(OCTOSPI_BASE + 0x0C)) /* Device Configuration register 2 */
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#define OCTOSPI_DCR3 (*(volatile uint32_t *)(OCTOSPI_BASE + 0x10)) /* Device Configuration register 3 */
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#define OCTOSPI_DCR4 (*(volatile uint32_t *)(OCTOSPI_BASE + 0x14)) /* Device Configuration register 4 */
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#define OCTOSPI_SR (*(volatile uint32_t *)(OCTOSPI_BASE + 0x20)) /* Status register */
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#define OCTOSPI_FCR (*(volatile uint32_t *)(OCTOSPI_BASE + 0x24)) /* Flag Clear register */
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#define OCTOSPI_DLR (*(volatile uint32_t *)(OCTOSPI_BASE + 0x40)) /* Data Length register */
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#define OCTOSPI_AR (*(volatile uint32_t *)(OCTOSPI_BASE + 0x48)) /* Address register */
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#define OCTOSPI_DR (*(volatile uint8_t *)(OCTOSPI_BASE + 0x50)) /* Data register */
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#define OCTOSPI_DR32 (*(volatile uint32_t *)(OCTOSPI_BASE + 0x50)) /* Data register - 32 bit */
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#define OCTOSPI_PSMKR (*(volatile uint32_t *)(OCTOSPI_BASE + 0x80)) /* Polling Status Mask register */
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#define OCTOSPI_PSMAR (*(volatile uint32_t *)(OCTOSPI_BASE + 0x88)) /* Polling Status Match register */
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#define OCTOSPI_PIR (*(volatile uint32_t *)(OCTOSPI_BASE + 0x90)) /* Polling Interval register */
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#define OCTOSPI_CCR (*(volatile uint32_t *)(OCTOSPI_BASE + 0x100)) /* Communication Configuration register */
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#define OCTOSPI_TCR (*(volatile uint32_t *)(OCTOSPI_BASE + 0x108)) /* Timing Configuration register */
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#define OCTOSPI_IR (*(volatile uint32_t *)(OCTOSPI_BASE + 0x110)) /* Instruction register */
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#define OCTOSPI_ABR (*(volatile uint32_t *)(OCTOSPI_BASE + 0x120)) /* Alternate Bytes register */
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#define OCTOSPI_LPTR (*(volatile uint32_t *)(OCTOSPI_BASE + 0x130)) /* Low Power Timeout register */
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#define OCTOSPI_CR_FMODE_MASK (0x3 << 28)
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#define OCTOSPI_CR_FMODE(fmode) (((fmode) & 0x3) << 28) /* Functional Mode (0=indirect write, 1=indirect read, 2=auto poll, 3=mem mapped) */
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#define OCTOSPI_CR_FTIE (1 << 18) /* FIFO threshold interrupt enable */
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#define OCTOSPI_CR_TCIE (1 << 17) /* Transfer complete interrupt enable */
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#define OCTOSPI_CR_FTHRES_MASK (0x1F << 8)
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#define OCTOSPI_CR_FTHRES(thr) ((((thr)-1) & 0x1F) << 8) /* FIFO threshold level */
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#define OCTOSPI_CR_FSEL (1 << 7) /* 0=Flash 1 or 1=Flash 2 */
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#define OCTOSPI_CR_ABORT (1 << 1) /* Abort request */
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#define OCTOSPI_CR_EN (1 << 0) /* Enable the QUADSPI */
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#define OCTOCPI_DCR1_MTYP_MASK (0x7 << 24)
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#define OCTOCPI_DCR1_MTYP(mtyp) (((mtyp) & 0x7) << 24) /* Memory type: 0=Micron, 1=Macronix, 2=Std, 3=Macronix RAM, 4=HyperBus mem, 5=HyperBus reg */
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#define OCTOSPI_DCR1_DEVSIZE_MASK (0x1F << 16)
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#define OCTOSPI_DCR1_DEVSIZE(dsz) (((dsz) & 0x1F) << 16) /* Device memory size (2 ^ (fsize + 1)). Example 16MB is 23 */
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#define OCTOSPI_DCR1_CSHT_MASK (0x3F << 8)
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#define OCTOSPI_DCR1_CSHT(csht) (((csht) & 0x3F) << 8) /* Chip select high time - Number of clock cycles (+1) nCS to remain high between commands */
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#define OCTOSPI_DCR1_CKMODE_3 (1 << 0) /* Clock mode 3 - clk high while nCS released */
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#define OCTOSPI_DCR1_CKMODE_0 (0) /* Clock mode 0 - clk low while nCS released */
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#define OCTOSPI_DCR2_PRESCALER_MASK (0xFF << 0)
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#define OCTOSPI_DCR2_PRESCALER(pre) ((((pre)-1) & 0xFF) << 0) /* Clock prescaler: quadspi_ker_ck/pre+1 */
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#define OCTOSPI_SR_TCF (1 << 1) /* Transfer complete flag - set in indirect mode when the programmed number of data has been transferred */
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#define OCTOSPI_SR_FTF (1 << 2) /* FIFO threshold flag */
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#define OCTOSPI_SR_BUSY (1 << 5) /* Busy - operation is ongoing when set */
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#define OCTOSPI_SR_FLEVEL(sr) (((sr) >> 8) & 0x3F) /* FIFO level */
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#define OCTOSPI_CCR_SIOO (1 << 31) /* Send instruction only once mode */
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#define OCTOSPI_CCR_DDTR (1 << 27) /* Data Double transfer rate mode */
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#define OCTOSPI_CCR_DMODE_MASK (0x7 << 24)
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#define OCTOSPI_CCR_DMODE(dmode) (((dmode) & 0x7) << 24) /* Data mode (0=no data, 1=data on single line, 2=data on two lines, 3=data on four lines, 4=data on eight lines) */
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#define OCTOSPI_CCR_ABSIZE_MASK (0x3 << 20)
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#define OCTOSPI_CCR_ABSIZE(absz) (((absz) & 0x3) << 20) /* Alternate bytes size */
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#define OCTOSPI_CCR_ABDTR (1 << 19) /* Alternate bytes Double transfer rate mode */
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#define OCTOSPI_CCR_ABMODE_MASK (0x7 << 16)
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#define OCTOSPI_CCR_ABMODE(abm) (((abm) & 0x7) << 16) /* Alternate bytes mode (0=no alt data, 1=alt on single line, 2=alt on two lines, 3=alt on four lines, 4=alt on eight lines) */
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#define OCTOSPI_CCR_ADSIZE_MASK (0x3 << 12)
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#define OCTOSPI_CCR_ADSIZE(sz) (((sz) & 0x3) << 12) /* Address bytes size (0=8-bit, 1=16-bit, 2=24-bit, 3=32-bit) */
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#define OCTOSPI_CCR_ADMODE_MASK (0x7 << 8)
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#define OCTOSPI_CCR_ADMODE(adm) (((adm) & 0x7) << 8) /* Address mode (0=no addr, 1=addr on single line, 2=addr on two lines, 3=addr on four lines, 4=addr on eight lines) */
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#define OCTOSPI_CCR_ISIZE_MASK (0x3 << 4)
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#define OCTOSPI_CCR_ISIZE(sz) (((sz) & 0x3) << 4) /* Instruction size (0=8-bit, 1=16-bit, 2=24-bit, 3=32-bit) */
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#define OCTOSPI_CCR_IMODE_MASK (0x7 << 0)
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#define OCTOSPI_CCR_IMODE(imode) (((imode) & 0x7) << 0) /* Instruction mode (0=no instr, 1=instr on single line, 2=instr on two lines, 3=instr on four lines, 4=instr on eight lines) */
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#define OCTOSPI_TCR_SSHIFT (1 << 30) /* Sample shift 1=1/2 cycle shift */
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#define OCTOSPI_TCR_DHQC (1 << 28) /* Delay the data output by 1/4 of clock cycle */
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#define OCTOSPI_TCR_DCYC_MASK (0x1F << 0)
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#define OCTOSPI_TCR_DCYC(dcyc) (((dcyc) & 0x1F) << 0) /* Number of dummy cycles */
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#endif /* !SPI_DRV_STM32_H_INCLUDED */
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