mirror of https://github.com/wolfSSL/wolfssl.git
initial attempt for MDK-ARM/LPC43xx:
kojo
parent
c2a82bce3d
commit
da342ea079
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@ -81,3 +81,4 @@ cov-int
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cyassl.tgz
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cyassl.tgz
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*.log
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*.log
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*.trs
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*.trs
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IDE\MDK-ARM\Projects
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@ -78,7 +78,7 @@
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// <h>STM32 Hardware Crypt
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// <h>STM32 Hardware Crypt
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// <e>STM32F2 Hardware RNG
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// <e>STM32F2 Hardware RNG
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#define MDK_CONF_STM32F2_RNG 1
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#define MDK_CONF_STM32F2_RNG 0
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#if MDK_CONF_STM32F2_RNG == 1
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#if MDK_CONF_STM32F2_RNG == 1
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#define STM32F2_RNG
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#define STM32F2_RNG
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#else
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#else
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@ -76,7 +76,7 @@
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// <h>STM32 Hardware Crypt
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// <h>STM32 Hardware Crypt
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// <e>STM32F2 Hardware RNG
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// <e>STM32F2 Hardware RNG
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#define MDK_CONF_STM32F2_RNG 1
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#define MDK_CONF_STM32F2_RNG 0
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#if MDK_CONF_STM32F2_RNG == 1
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#if MDK_CONF_STM32F2_RNG == 1
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#define STM32F2_RNG
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#define STM32F2_RNG
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#else
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#else
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@ -99,7 +99,7 @@
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// </h>
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// </h>
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// <h>STM32 Hardware Crypt
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// <h>STM32 Hardware Crypt
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// <e>STM32F2 Hardware RNG
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// <e>STM32F2 Hardware RNG
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#define MDK_CONF_STM32F2_RNG 1
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#define MDK_CONF_STM32F2_RNG 0
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#if MDK_CONF_STM32F2_RNG == 1
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#if MDK_CONF_STM32F2_RNG == 1
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#define STM32F2_RNG
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#define STM32F2_RNG
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#else
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#else
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@ -127,19 +127,19 @@
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// </e>
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// </e>
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// <e>CertGen
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// <e>CertGen
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#define MDK_CONF_CERT_GEN 0
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#define MDK_CONF_CERT_GEN 1
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#if MDK_CONF_CERT_GEN == 1
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#if MDK_CONF_CERT_GEN == 1
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#define CYASSL_CERT_GEN
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#define CYASSL_CERT_GEN
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#endif
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#endif
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// </e>
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// </e>
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// <e>KeyGen
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// <e>KeyGen
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#define MDK_CONF_KEY_GEN 0
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#define MDK_CONF_KEY_GEN 1
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#if MDK_CONF_KEY_GEN == 1
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#if MDK_CONF_KEY_GEN == 1
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#define CYASSL_KEY_GEN
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#define CYASSL_KEY_GEN
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#endif
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#endif
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// </e>
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// </e>
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// <e>CRL
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// <e>CRL
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#define MDK_CONF_DER_LOAD 0
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#define MDK_CONF_DER_LOAD 1
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#if MDK_CONF_DER_LOAD == 1
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#if MDK_CONF_DER_LOAD == 1
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#define CYASSL_DER_LOAD
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#define CYASSL_DER_LOAD
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#endif
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#endif
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@ -160,7 +160,7 @@
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// <h>MD5, SHA, SHA-256, AES, RC4, ASN, RSA
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// <h>MD5, SHA, SHA-256, AES, RC4, ASN, RSA
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// </h>
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// </h>
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// <e>MD2
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// <e>MD2
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#define MDK_CONF_MD2 0
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#define MDK_CONF_MD2 1
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#if MDK_CONF_MD2 == 1
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#if MDK_CONF_MD2 == 1
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#define CYASSL_MD2
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#define CYASSL_MD2
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#endif
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#endif
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@ -173,13 +173,13 @@
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// </e>
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// </e>
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// <e>SHA-384
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// <e>SHA-384
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// <i>This has to be with SHA512
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// <i>This has to be with SHA512
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#define MDK_CONF_SHA384 0
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#define MDK_CONF_SHA384 1
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#if MDK_CONF_SHA384 == 1
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#if MDK_CONF_SHA384 == 1
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#define CYASSL_SHA384
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#define CYASSL_SHA384
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#endif
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#endif
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// </e>
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// </e>
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// <e>SHA-512
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// <e>SHA-512
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#define MDK_CONF_SHA512 0
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#define MDK_CONF_SHA512 1
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#if MDK_CONF_SHA512 == 1
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#if MDK_CONF_SHA512 == 1
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#define CYASSL_SHA512
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#define CYASSL_SHA512
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#endif
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#endif
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@ -197,7 +197,7 @@
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#endif
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#endif
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// </e>
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// </e>
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// <e>HC128
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// <e>HC128
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#define MDK_CONF_HC128 0
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#define MDK_CONF_HC128 1
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#if MDK_CONF_HC128 == 1
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#if MDK_CONF_HC128 == 1
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#define HAVE_HC128
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#define HAVE_HC128
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#endif
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#endif
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@ -210,7 +210,7 @@
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// </e>
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// </e>
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// <e>AEAD
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// <e>AEAD
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#define MDK_CONF_AEAD 0
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#define MDK_CONF_AEAD 1
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#if MDK_CONF_AEAD == 1
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#if MDK_CONF_AEAD == 1
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#define HAVE_AEAD
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#define HAVE_AEAD
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#endif
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#endif
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@ -222,7 +222,7 @@
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#endif
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#endif
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// </e>
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// </e>
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// <e>CAMELLIA
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// <e>CAMELLIA
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#define MDK_CONF_CAMELLIA 0
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#define MDK_CONF_CAMELLIA 1
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#if MDK_CONF_CAMELLIA == 1
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#if MDK_CONF_CAMELLIA == 1
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#define HAVE_CAMELLIA
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#define HAVE_CAMELLIA
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#endif
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#endif
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@ -261,13 +261,13 @@
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#endif
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#endif
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// </e>
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// </e>
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// <e>AESCCM (Turn off Hardware Crypt)
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// <e>AESCCM (Turn off Hardware Crypt)
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#define MDK_CONF_AESCCM 0
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#define MDK_CONF_AESCCM 1
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#if MDK_CONF_AESCCM == 1
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#if MDK_CONF_AESCCM == 1
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#define HAVE_AESCCM
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#define HAVE_AESCCM
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#endif
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#endif
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// </e>
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// </e>
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// <e>AESGCM (Turn off Hardware Crypt)
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// <e>AESGCM (Turn off Hardware Crypt)
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#define MDK_CONF_AESGCM 0
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#define MDK_CONF_AESGCM 1
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#if MDK_CONF_AESGCM == 1
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#if MDK_CONF_AESGCM == 1
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#define HAVE_AESGCM
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#define HAVE_AESGCM
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#define BUILD_AESGCM
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#define BUILD_AESGCM
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@ -59,7 +59,7 @@ unsigned long inet_addr(const char *cp)
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/*** tcp_connect is actually associated with following syassl_tcp_connect. ***/
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/*** tcp_connect is actually associated with following syassl_tcp_connect. ***/
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int Cyassl_connect(int sd, const struct sockaddr* sa, int sz)
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int Cyassl_connect(int sd, const struct sockaddr* sa, int sz)
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{
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{
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int ret ;
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int ret = 0 ;
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#if defined(CYASSL_KEIL_TCP_NET)
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#if defined(CYASSL_KEIL_TCP_NET)
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SOCKADDR_IN addr ;
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SOCKADDR_IN addr ;
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@ -86,7 +86,7 @@ int Cyassl_connect(int sd, const struct sockaddr* sa, int sz)
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int Cyassl_accept(int sd, struct sockaddr *addr, int *addrlen)
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int Cyassl_accept(int sd, struct sockaddr *addr, int *addrlen)
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{
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{
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int ret ;
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int ret = 0 ;
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#if defined(CYASSL_KEIL_TCP_NET)
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#if defined(CYASSL_KEIL_TCP_NET)
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while(1) {
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while(1) {
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@ -110,7 +110,7 @@ int Cyassl_accept(int sd, struct sockaddr *addr, int *addrlen)
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int Cyassl_recv(int sd, void *buf, size_t len, int flags)
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int Cyassl_recv(int sd, void *buf, size_t len, int flags)
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{
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{
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int ret ;
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int ret = 0;
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#if defined(CYASSL_KEIL_TCP_NET)
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#if defined(CYASSL_KEIL_TCP_NET)
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while(1) {
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while(1) {
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#undef recv /* Go to KEIL TCPnet recv */
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#undef recv /* Go to KEIL TCPnet recv */
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@ -132,7 +132,7 @@ int Cyassl_recv(int sd, void *buf, size_t len, int flags)
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int Cyassl_send(int sd, const void *buf, size_t len, int flags)
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int Cyassl_send(int sd, const void *buf, size_t len, int flags)
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{
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{
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int ret ;
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int ret = 0 ;
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#if defined(CYASSL_KEIL_TCP_NET)
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#if defined(CYASSL_KEIL_TCP_NET)
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while(1) {
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while(1) {
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}
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}
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#endif
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#endif
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struct tm *Cyassl_MDK_gmtime(const time_t *c)
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{
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RTC_TimeTypeDef RTC_Time ;
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RTC_DateTypeDef RTC_Date ;
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static struct tm date ;
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RTC_GetTime(RTC_Format_BIN, &RTC_Time) ;
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RTC_GetDate(RTC_Format_BIN, &RTC_Date) ;
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date.tm_year = RTC_Date.RTC_Year + 100 ;
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date.tm_mon = RTC_Date.RTC_Month - 1 ;
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date.tm_mday = RTC_Date.RTC_Date ;
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date.tm_hour = RTC_Time.RTC_Hours ;
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date.tm_min = RTC_Time.RTC_Minutes ;
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date.tm_sec = RTC_Time.RTC_Seconds ;
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#if defined(DEBUG_CYASSL)
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{
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char msg[100] ;
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sprintf(msg, "Debug::Cyassl_KEIL_gmtime(DATE=/%4d/%02d/%02d TIME=%02d:%02d:%02d)\n",
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RTC_Date.RTC_Year+2000, RTC_Date.RTC_Month, RTC_Date.RTC_Date,
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RTC_Time.RTC_Hours, RTC_Time.RTC_Minutes, RTC_Time.RTC_Seconds) ;
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CYASSL_MSG(msg) ;
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}
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#endif
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return(&date) ;
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}
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double current_time()
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{
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return ((double)TIM2->CNT/1000000.0) ;
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}
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extern int getkey(void) ;
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extern int getkey(void) ;
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extern int sendchar(int c) ;
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extern int sendchar(int c) ;
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extern int select(int nfds, fd_set *readfds, fd_set *writefds,
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extern int select(int nfds, fd_set *readfds, fd_set *writefds,
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fd_set *exceptfds, const struct timeval *timeout);
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fd_set *exceptfds, const struct timeval *timeout);
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/* CyaSSL MDK-ARM time functions */
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/** KEIL-RL gmtime ****/
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#include <time.h>
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#include <time.h>
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#include "stm32f2xx_rtc.h"
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struct tm *Cyassl_MDK_gmtime(const time_t *c) ;
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extern struct tm *gmtime(const time_t *timer);
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extern struct tm *Cyassl_MDK_gmtime(const time_t *timer);
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extern double current_time(void) ;
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extern double current_time(void) ;
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#endif /* CYASSL_KEIL_RL_H */
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#endif /* CYASSL_KEIL_RL_H */
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#include <stdio.h>
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#include <stdio.h>
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#include "cyassl_MDK_ARM.h"
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#include "cyassl_MDK_ARM.h"
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#include "stm32f2xx_tim.h"
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#include "stm32f2xx_rcc.h"
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/*-----------------------------------------------------------------------------
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/*-----------------------------------------------------------------------------
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* Initialize a Flash Memory Card
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* Initialize a Flash Memory Card
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*----------------------------------------------------------------------------*/
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*----------------------------------------------------------------------------*/
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}
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}
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#endif
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#endif
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/*-----------------------------------------------------------------------------
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* initialize RTC
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*----------------------------------------------------------------------------*/
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#include "stm32f2xx_rtc.h"
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#include "stm32f2xx_rcc.h"
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#include "stm32f2xx_pwr.h"
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static init_RTC()
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{
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RTC_InitTypeDef RTC_InitStruct ;
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RTC_TimeTypeDef RTC_Time ;
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RTC_DateTypeDef RTC_Date ;
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/* Enable the PWR clock */
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
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/* Allow access to RTC */
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PWR_BackupAccessCmd(ENABLE);
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/***Configures the External Low Speed oscillator (LSE)****/
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RCC_LSEConfig(RCC_LSE_ON);
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/* Wait till LSE is ready */
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while(RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET)
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{
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}
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/* Select the RTC Clock Source */
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RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE);
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/* Enable the RTC Clock */
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RCC_RTCCLKCmd(ENABLE);
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/* Wait for RTC APB registers synchronisation */
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RTC_WaitForSynchro();
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/* Calendar Configuration with LSI supposed at 32KHz */
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RTC_InitStruct.RTC_AsynchPrediv = 0x7F;
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RTC_InitStruct.RTC_SynchPrediv = 0xFF;
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RTC_InitStruct.RTC_HourFormat = RTC_HourFormat_24;
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RTC_Init(&RTC_InitStruct);
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RTC_GetTime(RTC_Format_BIN, &RTC_Time) ;
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RTC_GetDate(RTC_Format_BIN, &RTC_Date) ;
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}
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/*-----------------------------------------------------------------------------
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* initialize TIM
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*----------------------------------------------------------------------------*/
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void init_timer()
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{
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TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure ;
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE) ;
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TIM_TimeBaseStructInit(&TIM_TimeBaseStructure);
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TIM_TimeBaseStructure.TIM_Prescaler = 60;
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TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
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TIM_TimeBaseStructure.TIM_Period = 0xffffffff;
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TIM_TimeBaseStructure.TIM_ClockDivision = 0;
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TIM_TimeBaseStructure.TIM_RepetitionCounter = 0;
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TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
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TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure) ;
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TIM_Cmd(TIM2, ENABLE) ;
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}
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#if defined(HAVE_KEIL_RTX) && defined(CYASSL_MDK_SHELL)
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#if defined(HAVE_KEIL_RTX) && defined(CYASSL_MDK_SHELL)
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#define SHELL_STACKSIZE 1000
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#define SHELL_STACKSIZE 1000
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static unsigned char Shell_stack[SHELL_STACKSIZE] ;
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static unsigned char Shell_stack[SHELL_STACKSIZE] ;
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@ -193,11 +118,12 @@ void main_task (void)
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shell_main() ;
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shell_main() ;
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#endif
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#endif
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#else
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#else
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/************************************/
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/************************************/
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/*** USER APPLICATION HERE ***/
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/*** USER APPLICATION HERE ***/
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/************************************/
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/************************************/
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printf("USER LOGIC STARTED\n") ;
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#endif
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#endif
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#ifdef HAVE_KEIL_RTX
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#ifdef HAVE_KEIL_RTX
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@ -217,16 +143,19 @@ void main_task (void)
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/*** main entry ***/
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/*** main entry ***/
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extern void init_time(void) ;
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extern void SystemInit(void);
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int main() {
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int main() {
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/* stm32_Init (); STM32 setup */
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SystemInit();
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SER_Init() ;
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#if !defined(NO_FILESYSTEM)
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#if !defined(NO_FILESYSTEM)
|
||||||
init_card () ; /* initializing SD card */
|
init_card () ; /* initializing SD card */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
init_RTC() ;
|
init_time() ;
|
||||||
init_timer() ;
|
|
||||||
SER_Init() ;
|
|
||||||
|
|
||||||
#if defined(DEBUG_CYASSL)
|
#if defined(DEBUG_CYASSL)
|
||||||
printf("Turning ON Debug message\n") ;
|
printf("Turning ON Debug message\n") ;
|
||||||
|
|
|
||||||
|
|
@ -384,39 +384,6 @@ static void ipaddr_comm(void *args)
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
static void time_main(void *args)
|
|
||||||
{
|
|
||||||
char * datetime ;
|
|
||||||
RTC_TimeTypeDef RTC_Time ;
|
|
||||||
RTC_DateTypeDef RTC_Date ;
|
|
||||||
int year ;
|
|
||||||
if( args == NULL || ((func_args *)args)->argc == 1) {
|
|
||||||
RTC_GetTime(RTC_Format_BIN, &RTC_Time) ;
|
|
||||||
RTC_GetDate(RTC_Format_BIN, &RTC_Date) ;
|
|
||||||
printf("Date: %d/%d/%d, Time: %02d:%02d:%02d\n",
|
|
||||||
RTC_Date.RTC_Month, RTC_Date.RTC_Date, RTC_Date.RTC_Year+2000,
|
|
||||||
RTC_Time.RTC_Hours, RTC_Time.RTC_Minutes, RTC_Time.RTC_Seconds) ;
|
|
||||||
} else if(((func_args *)args)->argc == 3 &&
|
|
||||||
((func_args *)args)->argv[1][0] == '-' &&
|
|
||||||
((func_args *)args)->argv[1][1] == 'd' ) {
|
|
||||||
datetime = ((func_args *)args)->argv[2];
|
|
||||||
sscanf(datetime, "%d/%d/%d",
|
|
||||||
(int *)&RTC_Date.RTC_Month, (int *)&RTC_Date.RTC_Date, &year) ;
|
|
||||||
RTC_Date.RTC_Year = year - 2000 ;
|
|
||||||
RTC_Date.RTC_WeekDay = 0 ;
|
|
||||||
RTC_SetDate(RTC_Format_BIN, &RTC_Date) ;
|
|
||||||
} else if(((func_args *)args)->argc == 3 &&
|
|
||||||
((func_args *)args)->argv[1][0] == '-' &&
|
|
||||||
((func_args *)args)->argv[1][1] == 't' ) {
|
|
||||||
datetime = ((func_args *)args)->argv[2];
|
|
||||||
sscanf(datetime, "%d:%d:%d",
|
|
||||||
(int *)&RTC_Time.RTC_Hours,
|
|
||||||
(int *)&RTC_Time.RTC_Minutes,
|
|
||||||
(int *)&RTC_Time.RTC_Seconds
|
|
||||||
) ;
|
|
||||||
RTC_SetTime(RTC_Format_BIN, &RTC_Time) ;
|
|
||||||
} else printf("Invalid argument\n") ;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
#if defined(HAVE_KEIL_RTX)
|
#if defined(HAVE_KEIL_RTX)
|
||||||
|
|
|
||||||
|
|
@ -1,387 +1,401 @@
|
||||||
/*----------------------------------------------------------------------------
|
/*----------------------------------------------------------------------------
|
||||||
* RL-ARM - FlashFS
|
* RL-ARM - FlashFS
|
||||||
*----------------------------------------------------------------------------
|
*----------------------------------------------------------------------------
|
||||||
* Name: FILE_CONFIG.C
|
* Name: FILE_CONFIG.C
|
||||||
* Purpose: Configuration of RL FlashFS by user
|
* Purpose: Configuration of RL FlashFS by user
|
||||||
* Rev.: V4.50
|
* Rev.: V4.70
|
||||||
*----------------------------------------------------------------------------
|
*----------------------------------------------------------------------------
|
||||||
* This code is part of the RealView Run-Time Library.
|
* This code is part of the RealView Run-Time Library.
|
||||||
* Copyright (c) 2004-2012 KEIL - An ARM Company. All rights reserved.
|
* Copyright (c) 2004-2013 KEIL - An ARM Company. All rights reserved.
|
||||||
*---------------------------------------------------------------------------*/
|
*---------------------------------------------------------------------------*/
|
||||||
|
|
||||||
#include <File_Config.h>
|
#include <File_Config.h>
|
||||||
|
|
||||||
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
|
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
|
||||||
//
|
//
|
||||||
// <h>File System
|
// <h>File System
|
||||||
// ==============
|
// ==============
|
||||||
// <i> Define File System global parameters
|
// <i> Define File System global parameters
|
||||||
|
|
||||||
// <o>Number of open files <4-16>
|
// <o>Number of open files <4-16>
|
||||||
// <i>Define number of files that can be
|
// <i>Define number of files that can be
|
||||||
// <i>opened at the same time.
|
// <i>opened at the same time.
|
||||||
// <i>Default: 8
|
// <i>Default: 8
|
||||||
#define N_FILES 6
|
#define N_FILES 6
|
||||||
|
|
||||||
// <o>CPU Clock Frequency [Hz]<0-1000000000>
|
// <o>FAT Name Cache Size <0-1000000>
|
||||||
// <i>Define the CPU Clock frequency used for
|
// <i>Define number of cached FAT file or directory names.
|
||||||
// <i>flash programming and erasing.
|
// <i>48 bytes of RAM is required for each cached name.
|
||||||
#define CPU_CLK 120000000
|
#define FAT_NAME_CACNT 0
|
||||||
|
|
||||||
// </h>
|
// <e>Relocate FAT Name Cache Buffer
|
||||||
// <e>Flash Drive
|
// <i>Locate Cache Buffer at a specific address.
|
||||||
// ==============
|
#define FAT_NAME_RELOC 0
|
||||||
// <i>Enable Embedded Flash Drive [F:]
|
|
||||||
#define FL0_EN 0
|
// <o>Base address <0x0000-0xFFFFFE00:0x200>
|
||||||
|
// <i>Define the Cache buffer base address.
|
||||||
// <o>Base address <0x0-0xFFFFF000:0x1000>
|
#define FAT_NAME_CADR 0x60000000
|
||||||
// <i>Define the target device Base address
|
|
||||||
// <i>Default: 0x80000000
|
// </e>
|
||||||
#define FL0_BADR 0x80000000
|
// <o>CPU Clock Frequency [Hz]<0-1000000000>
|
||||||
|
// <i>Define the CPU Clock frequency used for
|
||||||
// <o>Device Size <0x4000-0xFFFFF000:0x4000>
|
// <i>flash programming and erasing.
|
||||||
// <i>Define the size of Flash device in bytes
|
#define CPU_CLK 180000000
|
||||||
// <i>Default: 0x100000 (1MB)
|
|
||||||
#define FL0_SIZE 0x0200000
|
// </h>
|
||||||
|
// <e>Flash Drive
|
||||||
// <o>Content of Erased Memory <0=>0x00 <0xFF=>0xFF
|
// ==============
|
||||||
// <i>Define the initial value for erased Flash data
|
// <i>Enable Embedded Flash Drive [F:]
|
||||||
// <i>Default: 0xFF
|
#define FL0_EN 0
|
||||||
#define FL0_INITV 0xFF
|
|
||||||
|
// <o>Base address <0x0-0xFFFFF000:0x1000>
|
||||||
// <s.80>Device Description file
|
// <i>Define the target device Base address
|
||||||
// <i>Specify a file name with a relative path
|
// <i>Default: 0x80000000
|
||||||
// <i>Default: FS_FlashDev.h
|
#define FL0_BADR 0x80000000
|
||||||
#define FL0_HFILE "FS_FlashDev.h"
|
|
||||||
|
// <o>Device Size <0x4000-0xFFFFF000:0x4000>
|
||||||
// <q>Default Drive [F:]
|
// <i>Define the size of Flash device in bytes
|
||||||
// <i>Used when Drive letter not specified
|
// <i>Default: 0x100000 (1MB)
|
||||||
#define FL0_DEF 1
|
#define FL0_SIZE 0x0200000
|
||||||
|
|
||||||
// </e>
|
// <o>Content of Erased Memory <0=>0x00 <0xFF=>0xFF
|
||||||
// <e>SPI Flash Drive
|
// <i>Define the initial value for erased Flash data
|
||||||
// ==================
|
// <i>Default: 0xFF
|
||||||
// <i>Enable SPI Flash Drive [S:]
|
#define FL0_INITV 0xFF
|
||||||
#define SF0_EN 0
|
|
||||||
|
// <s.80>Device Description file
|
||||||
// <o>Device Size <0x10000-0xFFFFF000:0x8000>
|
// <i>Specify a file name with a relative path
|
||||||
// <i>Define the size of SPI Flash device in bytes
|
// <i>Default: FS_FlashDev.h
|
||||||
// <i>Default: 0x100000 (1MB)
|
#define FL0_HFILE "FS_FlashDev.h"
|
||||||
#define SF0_SIZE 0x0200000
|
|
||||||
|
// <q>Default Drive [F:]
|
||||||
// <o>Content of Erased Memory <0=>0x00 <0xFF=>0xFF
|
// <i>Used when Drive letter not specified
|
||||||
// <i>Define the initial value for erased Flash data
|
#define FL0_DEF 1
|
||||||
// <i>Default: 0xFF
|
|
||||||
#define SF0_INITV 0xFF
|
// </e>
|
||||||
|
// <e>SPI Flash Drive
|
||||||
// <s.80>Device Description file
|
// ==================
|
||||||
// <i>Specify a file name with a relative path
|
// <i>Enable SPI Flash Drive [S:]
|
||||||
// <i>Default: FS_SPI_FlashDev.h
|
#define SF0_EN 0
|
||||||
#define SF0_HFILE "FS_SPI_FlashDev.h"
|
|
||||||
|
// <o>Device Size <0x10000-0xFFFFF000:0x8000>
|
||||||
// <q>Default Drive [S:]
|
// <i>Define the size of SPI Flash device in bytes
|
||||||
// <i>Used when Drive letter not specified
|
// <i>Default: 0x100000 (1MB)
|
||||||
#define SF0_DEF 0
|
#define SF0_SIZE 0x0200000
|
||||||
|
|
||||||
// </e>
|
// <o>Content of Erased Memory <0=>0x00 <0xFF=>0xFF
|
||||||
// <e>RAM Drive
|
// <i>Define the initial value for erased Flash data
|
||||||
// ============
|
// <i>Default: 0xFF
|
||||||
// <i>Enable Embedded RAM Drive [R:]
|
#define SF0_INITV 0xFF
|
||||||
#define RAM0_EN 0
|
|
||||||
|
// <s.80>Device Description file
|
||||||
// <o>Device Size <0x4000-0xFFFFF000:0x4000>
|
// <i>Specify a file name with a relative path
|
||||||
// <i>Define the size of RAM device in bytes
|
// <i>Default: FS_SPI_FlashDev.h
|
||||||
// <i>Default: 0x40000
|
#define SF0_HFILE "FS_SPI_FlashDev.h"
|
||||||
#define RAM0_SIZE 0x004000
|
|
||||||
|
// <q>Default Drive [S:]
|
||||||
// <o>Number of Sectors <8=>8 <16=>16 <32=>32 <64=>64 <128=>128
|
// <i>Used when Drive letter not specified
|
||||||
// <i>Define number of virtual sectors for RAM device
|
#define SF0_DEF 0
|
||||||
// <i>Default: 32
|
|
||||||
#define RAM0_NSECT 64
|
// </e>
|
||||||
|
// <e>RAM Drive
|
||||||
// <e>Relocate Device Buffer
|
// ============
|
||||||
// <i>Locate RAM Device Buffer at a specific address.
|
// <i>Enable Embedded RAM Drive [R:]
|
||||||
// <i>If not enabled, the linker selects base address.
|
#define RAM0_EN 0
|
||||||
#define RAM0_RELOC 1
|
|
||||||
|
// <o>Device Size <0x4000-0xFFFFF000:0x4000>
|
||||||
// <o>Base address <0x0-0xFFFFF000:0x1000>
|
// <i>Define the size of RAM device in bytes
|
||||||
// <i>Define the target device Base address.
|
// <i>Default: 0x40000
|
||||||
// <i>Default: 0x81000000
|
#define RAM0_SIZE 0x004000
|
||||||
#define RAM0_BADR 0x81010000
|
|
||||||
|
// <o>Number of Sectors <8=>8 <16=>16 <32=>32 <64=>64 <128=>128
|
||||||
// </e>
|
// <i>Define number of virtual sectors for RAM device
|
||||||
// <q>Default Drive [R:]
|
// <i>Default: 32
|
||||||
// <i>Used when Drive letter not specified
|
#define RAM0_NSECT 64
|
||||||
#define RAM0_DEF 0
|
|
||||||
|
// <e>Relocate Device Buffer
|
||||||
// </e>
|
// <i>Locate RAM Device Buffer at a specific address.
|
||||||
// <e>Memory Card Drive 0
|
// <i>If not enabled, the linker selects base address.
|
||||||
// ======================
|
#define RAM0_RELOC 1
|
||||||
// <i>Enable Memory Card Drive [M0:]
|
|
||||||
#define MC0_EN 1
|
// <o>Base address <0x0-0xFFFFF000:0x1000>
|
||||||
|
// <i>Define the target device Base address.
|
||||||
// <o>Bus Mode <0=>SD-Native <1=>SPI
|
// <i>Default: 0x81000000
|
||||||
// <i>Define Memory Card bus interface mode.
|
#define RAM0_BADR 0x81010000
|
||||||
// <i>SD-Native mode needs MCI peripheral.
|
|
||||||
// <i>SPI mode uses SD Card in SPI mode.
|
// </e>
|
||||||
#define MC0_SPI 0
|
// <q>Default Drive [R:]
|
||||||
|
// <i>Used when Drive letter not specified
|
||||||
// <o>File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
|
#define RAM0_DEF 0
|
||||||
// <8=>8 KB <16=>16 KB <32=>32 KB
|
|
||||||
// <i>Define System Cache buffer size for file IO.
|
// </e>
|
||||||
// <i>Increase this number for faster r/w access.
|
// <e>Memory Card Drive 0
|
||||||
// <i>Default: 4 kB
|
// ======================
|
||||||
#define MC0_CASZ 16
|
// <i>Enable Memory Card Drive [M0:]
|
||||||
|
#define MC0_EN 1
|
||||||
// <e>Relocate Cache Buffer
|
|
||||||
// <i>Locate Cache Buffer at a specific address.
|
// <o>Bus Mode <0=>SD-Native <1=>SPI
|
||||||
// <i>Some devices like NXP LPC23xx require a Cache buffer
|
// <i>Define Memory Card bus interface mode.
|
||||||
// <i>for DMA transfer located at specific address.
|
// <i>SD-Native mode needs MCI peripheral.
|
||||||
#define MC0_RELOC 0
|
// <i>SPI mode uses SD Card in SPI mode.
|
||||||
|
#define MC0_SPI 0
|
||||||
// <o>Base address <0x0000-0xFFFFFE00:0x200>
|
|
||||||
// <i>Define the Cache buffer base address.
|
// <o>File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
|
||||||
// <i>For LPC23xx/24xx devices this is USB RAM
|
// <8=>8 KB <16=>16 KB <32=>32 KB
|
||||||
// <i>starting at 0x7FD00000.
|
// <i>Define System Cache buffer size for file IO.
|
||||||
#define MC0_CADR 0x7FD00000
|
// <i>Increase this number for faster r/w access.
|
||||||
|
// <i>Default: 4 kB
|
||||||
// </e>
|
#define MC0_CASZ 4
|
||||||
// <q>FAT Journal
|
|
||||||
// <i>Enable FAT Journal in order to guarantee
|
// <e>Relocate Cache Buffer
|
||||||
// <i>fail-safe FAT file system operation.
|
// <i>Locate Cache Buffer at a specific address.
|
||||||
#define MC0_FSJ 0
|
// <i>Some devices like NXP LPC23xx require a Cache buffer
|
||||||
|
// <i>for DMA transfer located at specific address.
|
||||||
// <q>Default Drive [M0:]
|
#define MC0_RELOC 0
|
||||||
// <i>Used when Drive letter not specified
|
|
||||||
#define MC0_DEF 1
|
// <o>Base address <0x0000-0xFFFFFE00:0x200>
|
||||||
|
// <i>Define the Cache buffer base address.
|
||||||
// </e>
|
// <i>For LPC23xx/24xx devices this is USB RAM
|
||||||
// <e>Memory Card Drive 1
|
// <i>starting at 0x7FD00000.
|
||||||
// ======================
|
#define MC0_CADR 0x7FD00000
|
||||||
// <i>Enable Memory Card Drive [M1:]
|
|
||||||
#define MC1_EN 0
|
// </e>
|
||||||
|
// <q>FAT Journal
|
||||||
// <o>Bus Mode <0=>SD-Native <1=>SPI
|
// <i>Enable FAT Journal in order to guarantee
|
||||||
// <i>Define Memory Card bus interface mode.
|
// <i>fail-safe FAT file system operation.
|
||||||
// <i>SD-Native mode needs MCI peripheral.
|
#define MC0_FSJ 0
|
||||||
// <i>SPI mode uses SD Card in SPI mode.
|
|
||||||
#define MC1_SPI 1
|
// <q>Default Drive [M0:]
|
||||||
|
// <i>Used when Drive letter not specified
|
||||||
// <o>File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
|
#define MC0_DEF 1
|
||||||
// <8=>8 KB <16=>16 KB <32=>32 KB
|
|
||||||
// <i>Define System Cache buffer size for file IO.
|
// </e>
|
||||||
// <i>Increase this number for faster r/w access.
|
// <e>Memory Card Drive 1
|
||||||
// <i>Default: 4 kB
|
// ======================
|
||||||
#define MC1_CASZ 0
|
// <i>Enable Memory Card Drive [M1:]
|
||||||
|
#define MC1_EN 0
|
||||||
// <e>Relocate Cache Buffer
|
|
||||||
// <i>Locate Cache Buffer at a specific address.
|
// <o>Bus Mode <0=>SD-Native <1=>SPI
|
||||||
// <i>Some devices like NXP LPC23xx require a Cache buffer
|
// <i>Define Memory Card bus interface mode.
|
||||||
// <i>for DMA transfer located at specific address.
|
// <i>SD-Native mode needs MCI peripheral.
|
||||||
#define MC1_RELOC 0
|
// <i>SPI mode uses SD Card in SPI mode.
|
||||||
|
#define MC1_SPI 1
|
||||||
// <o>Base address <0x0000-0xFFFFFE00:0x200>
|
|
||||||
// <i>Define the Cache buffer base address.
|
// <o>File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
|
||||||
// <i>For LPC23xx/24xx devices this is USB RAM
|
// <8=>8 KB <16=>16 KB <32=>32 KB
|
||||||
// <i>starting at 0x7FD00000.
|
// <i>Define System Cache buffer size for file IO.
|
||||||
#define MC1_CADR 0x7FD00000
|
// <i>Increase this number for faster r/w access.
|
||||||
|
// <i>Default: 4 kB
|
||||||
// </e>
|
#define MC1_CASZ 0
|
||||||
// <q>FAT Journal
|
|
||||||
// <i>Enable FAT Journal in order to guarantee
|
// <e>Relocate Cache Buffer
|
||||||
// <i>fail-safe FAT file system operation.
|
// <i>Locate Cache Buffer at a specific address.
|
||||||
#define MC1_FSJ 0
|
// <i>Some devices like NXP LPC23xx require a Cache buffer
|
||||||
|
// <i>for DMA transfer located at specific address.
|
||||||
// <q>Default Drive [M1:]
|
#define MC1_RELOC 0
|
||||||
// <i>Used when Drive letter not specified
|
|
||||||
#define MC1_DEF 0
|
// <o>Base address <0x0000-0xFFFFFE00:0x200>
|
||||||
|
// <i>Define the Cache buffer base address.
|
||||||
// </e>
|
// <i>For LPC23xx/24xx devices this is USB RAM
|
||||||
// <e>USB Flash Drive 0
|
// <i>starting at 0x7FD00000.
|
||||||
// ====================
|
#define MC1_CADR 0x7FD00000
|
||||||
// <i>Enable USB Flash Drive [U0:]
|
|
||||||
#define USB0_EN 0
|
// </e>
|
||||||
|
// <q>FAT Journal
|
||||||
// <o>File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
|
// <i>Enable FAT Journal in order to guarantee
|
||||||
// <8=>8 KB <16=>16 KB <32=>32 KB
|
// <i>fail-safe FAT file system operation.
|
||||||
// <i>Define System Cache buffer size for file IO.
|
#define MC1_FSJ 0
|
||||||
// <i>Increase this number for faster r/w access.
|
|
||||||
// <i>Default: 4 kB
|
// <q>Default Drive [M1:]
|
||||||
#define USB0_CASZ 8
|
// <i>Used when Drive letter not specified
|
||||||
|
#define MC1_DEF 0
|
||||||
// <q>FAT Journal
|
|
||||||
// <i>Enable FAT Journal in order to guarantee
|
// </e>
|
||||||
// <i>fail-safe FAT file system operation.
|
// <e>USB Flash Drive 0
|
||||||
#define USB0_FSJ 0
|
// ====================
|
||||||
|
// <i>Enable USB Flash Drive [U0:]
|
||||||
// <q>Default Drive [U0:]
|
#define USB0_EN 0
|
||||||
// <i>Used when Drive letter not specified
|
|
||||||
#define USB0_DEF 1
|
// <o>File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
|
||||||
|
// <8=>8 KB <16=>16 KB <32=>32 KB
|
||||||
// </e>
|
// <i>Define System Cache buffer size for file IO.
|
||||||
// <e>USB Flash Drive 1
|
// <i>Increase this number for faster r/w access.
|
||||||
// ====================
|
// <i>Default: 4 kB
|
||||||
// <i>Enable USB Flash Drive [U1:]
|
#define USB0_CASZ 8
|
||||||
#define USB1_EN 0
|
|
||||||
|
// <q>FAT Journal
|
||||||
// <o>File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
|
// <i>Enable FAT Journal in order to guarantee
|
||||||
// <8=>8 KB <16=>16 KB <32=>32 KB
|
// <i>fail-safe FAT file system operation.
|
||||||
// <i>Define System Cache buffer size for file IO.
|
#define USB0_FSJ 0
|
||||||
// <i>Increase this number for faster r/w access.
|
|
||||||
// <i>Default: 4 kB
|
// <q>Default Drive [U0:]
|
||||||
#define USB1_CASZ 8
|
// <i>Used when Drive letter not specified
|
||||||
|
#define USB0_DEF 0
|
||||||
// <q>FAT Journal
|
|
||||||
// <i>Enable FAT Journal in order to guarantee
|
// </e>
|
||||||
// <i>fail-safe FAT file system operation.
|
// <e>USB Flash Drive 1
|
||||||
#define USB1_FSJ 0
|
// ====================
|
||||||
|
// <i>Enable USB Flash Drive [U1:]
|
||||||
// <q>Default Drive [U1:]
|
#define USB1_EN 0
|
||||||
// <i>Used when Drive letter not specified
|
|
||||||
#define USB1_DEF 1
|
// <o>File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
|
||||||
|
// <8=>8 KB <16=>16 KB <32=>32 KB
|
||||||
// </e>
|
// <i>Define System Cache buffer size for file IO.
|
||||||
// <e>NAND Flash Drive 0
|
// <i>Increase this number for faster r/w access.
|
||||||
// ===================
|
// <i>Default: 4 kB
|
||||||
// <i>Enable NAND Flash Drive [N0:]
|
#define USB1_CASZ 8
|
||||||
#define NAND0_EN 0
|
|
||||||
|
// <q>FAT Journal
|
||||||
// <o>Page size <528=> 512 + 16 bytes
|
// <i>Enable FAT Journal in order to guarantee
|
||||||
// <2112=>2048 + 64 bytes
|
// <i>fail-safe FAT file system operation.
|
||||||
// <4224=>4096 + 128 bytes
|
#define USB1_FSJ 0
|
||||||
// <8448=>8192 + 256 bytes
|
|
||||||
// <i>Define program Page size in bytes (User + Spare area).
|
// <q>Default Drive [U1:]
|
||||||
#define NAND0_PGSZ 2112
|
// <i>Used when Drive letter not specified
|
||||||
|
#define USB1_DEF 0
|
||||||
// <o>Block Size <8=>8 pages <16=>16 pages <32=>32 pages
|
|
||||||
// <64=>64 pages <128=>128 pages <256=>256 pages
|
// </e>
|
||||||
// <i>Define number of pages in a block.
|
// <e>NAND Flash Drive 0
|
||||||
#define NAND0_PGCNT 64
|
// ===================
|
||||||
|
// <i>Enable NAND Flash Drive [N0:]
|
||||||
// <o>Device Size [blocks] <512-32768>
|
#define NAND0_EN 0
|
||||||
// <i>Define number of blocks in NAND Flash device.
|
|
||||||
#define NAND0_BLCNT 4096
|
// <o>Page size <528=> 512 + 16 bytes
|
||||||
|
// <2112=>2048 + 64 bytes
|
||||||
// <o>Page Caching <0=>OFF <1=>1 page <2=>2 pages <4=>4 pages
|
// <4224=>4096 + 128 bytes
|
||||||
// <8=>8 pages <16=>16 pages <32=>32 pages
|
// <8448=>8192 + 256 bytes
|
||||||
// <i>Define number of cached Pages.
|
// <i>Define program Page size in bytes (User + Spare area).
|
||||||
// <i>Default: 4 pages
|
#define NAND0_PGSZ 2112
|
||||||
#define NAND0_CAPG 2
|
|
||||||
|
// <o>Block Size <8=>8 pages <16=>16 pages <32=>32 pages
|
||||||
// <o>Block Indexing <0=>OFF <1=>1 block <2=>2 blocks <4=>4 blocks
|
// <64=>64 pages <128=>128 pages <256=>256 pages
|
||||||
// <8=>8 blocks <16=>16 blocks <32=>32 blocks
|
// <i>Define number of pages in a block.
|
||||||
// <64=>64 blocks <128=>128 blocks <256=>256 blocks
|
#define NAND0_PGCNT 64
|
||||||
// <i>Define number of indexed Flash Blocks.
|
|
||||||
// <i>Increase this number for better performance.
|
// <o>Device Size [blocks] <512-32768>
|
||||||
// <i>Default: 16 blocks
|
// <i>Define number of blocks in NAND Flash device.
|
||||||
#define NAND0_CABL 16
|
#define NAND0_BLCNT 4096
|
||||||
|
|
||||||
// <o>Software ECC <0=>None <1=>Hamming (SLC)
|
// <o>Page Caching <0=>OFF <1=>1 page <2=>2 pages <4=>4 pages
|
||||||
// <i>Enable software ECC calculation only,
|
// <8=>8 pages <16=>16 pages <32=>32 pages
|
||||||
// <i>if not supported by hardware.
|
// <i>Define number of cached Pages.
|
||||||
#define NAND0_SWECC 1
|
// <i>Default: 4 pages
|
||||||
|
#define NAND0_CAPG 2
|
||||||
// <o>File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
|
|
||||||
// <8=>8 KB <16=>16 KB <32=>32 KB
|
// <o>Block Indexing <0=>OFF <1=>1 block <2=>2 blocks <4=>4 blocks
|
||||||
// <i>Define System Cache buffer size for file IO.
|
// <8=>8 blocks <16=>16 blocks <32=>32 blocks
|
||||||
// <i>Increase this number for faster r/w access.
|
// <64=>64 blocks <128=>128 blocks <256=>256 blocks
|
||||||
// <i>Default: 4 kB
|
// <i>Define number of indexed Flash Blocks.
|
||||||
#define NAND0_CASZ 4
|
// <i>Increase this number for better performance.
|
||||||
|
// <i>Default: 16 blocks
|
||||||
// <e>Relocate Cache Buffers
|
#define NAND0_CABL 16
|
||||||
// <i>Use this option to locate Cache buffers
|
|
||||||
// <i>at specific address in RAM or SDRAM.
|
// <o>Software ECC <0=>None <1=>Hamming (SLC)
|
||||||
#define NAND0_RELOC 0
|
// <i>Enable software ECC calculation only,
|
||||||
|
// <i>if not supported by hardware.
|
||||||
// <o>Base address <0x0000-0xFFFFFE00:0x200>
|
#define NAND0_SWECC 1
|
||||||
// <i>Define base address for Cache Buffers.
|
|
||||||
#define NAND0_CADR 0x80000000
|
// <o>File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
|
||||||
|
// <8=>8 KB <16=>16 KB <32=>32 KB
|
||||||
// </e>
|
// <i>Define System Cache buffer size for file IO.
|
||||||
// <q>FAT Journal
|
// <i>Increase this number for faster r/w access.
|
||||||
// <i>Enable FAT Journal in order to guarantee
|
// <i>Default: 4 kB
|
||||||
// <i>fail-safe FAT file system operation.
|
#define NAND0_CASZ 4
|
||||||
#define NAND0_FSJ 0
|
|
||||||
|
// <e>Relocate Cache Buffers
|
||||||
// <q>Default Drive [N0:]
|
// <i>Use this option to locate Cache buffers
|
||||||
// <i>Used when Drive letter not specified
|
// <i>at specific address in RAM or SDRAM.
|
||||||
#define NAND0_DEF 0
|
#define NAND0_RELOC 0
|
||||||
|
|
||||||
// </e>
|
// <o>Base address <0x0000-0xFFFFFE00:0x200>
|
||||||
// <e>NAND Flash Drive 1
|
// <i>Define base address for Cache Buffers.
|
||||||
// ===================
|
#define NAND0_CADR 0x80000000
|
||||||
// <i>Enable NAND Flash Drive [N1:]
|
|
||||||
#define NAND1_EN 0
|
// </e>
|
||||||
|
// <q>FAT Journal
|
||||||
// <o>Page size <528=> 512 + 16 bytes
|
// <i>Enable FAT Journal in order to guarantee
|
||||||
// <2112=>2048 + 64 bytes
|
// <i>fail-safe FAT file system operation.
|
||||||
// <4224=>4096 + 128 bytes
|
#define NAND0_FSJ 0
|
||||||
// <8448=>8192 + 256 bytes
|
|
||||||
// <i>Define program Page size in bytes (User + Spare area).
|
// <q>Default Drive [N0:]
|
||||||
#define NAND1_PGSZ 2112
|
// <i>Used when Drive letter not specified
|
||||||
|
#define NAND0_DEF 0
|
||||||
// <o>Block Size <8=>8 pages <16=>16 pages <32=>32 pages
|
|
||||||
// <64=>64 pages <128=>128 pages <256=>256 pages
|
// </e>
|
||||||
// <i>Define number of pages in a block.
|
// <e>NAND Flash Drive 1
|
||||||
#define NAND1_PGCNT 32
|
// ===================
|
||||||
|
// <i>Enable NAND Flash Drive [N1:]
|
||||||
// <o>Device Size [blocks] <512-32768>
|
#define NAND1_EN 0
|
||||||
// <i>Define number of blocks in NAND Flash device.
|
|
||||||
#define NAND1_BLCNT 512
|
// <o>Page size <528=> 512 + 16 bytes
|
||||||
|
// <2112=>2048 + 64 bytes
|
||||||
// <o>Page Caching <0=>OFF <1=>1 page <2=>2 pages <4=>4 pages
|
// <4224=>4096 + 128 bytes
|
||||||
// <8=>8 pages <16=>16 pages <32=>32 pages
|
// <8448=>8192 + 256 bytes
|
||||||
// <i>Define number of cached Pages.
|
// <i>Define program Page size in bytes (User + Spare area).
|
||||||
// <i>Default: 4 pages
|
#define NAND1_PGSZ 2112
|
||||||
#define NAND1_CAPG 4
|
|
||||||
|
// <o>Block Size <8=>8 pages <16=>16 pages <32=>32 pages
|
||||||
// <o>Block Indexing <0=>OFF <1=>1 block <2=>2 blocks <4=>4 blocks
|
// <64=>64 pages <128=>128 pages <256=>256 pages
|
||||||
// <8=>8 blocks <16=>16 blocks <32=>32 blocks
|
// <i>Define number of pages in a block.
|
||||||
// <64=>64 blocks <128=>128 blocks <256=>256 blocks
|
#define NAND1_PGCNT 32
|
||||||
// <i>Define number of indexed Flash Blocks.
|
|
||||||
// <i>Increase this number for better performance.
|
// <o>Device Size [blocks] <512-32768>
|
||||||
// <i>Default: 16 blocks
|
// <i>Define number of blocks in NAND Flash device.
|
||||||
#define NAND1_CABL 16
|
#define NAND1_BLCNT 512
|
||||||
|
|
||||||
// <o>Software ECC <0=>None <1=>Hamming (SLC)
|
// <o>Page Caching <0=>OFF <1=>1 page <2=>2 pages <4=>4 pages
|
||||||
// <i>Enable software ECC calculation only,
|
// <8=>8 pages <16=>16 pages <32=>32 pages
|
||||||
// <i>if not supported by hardware.
|
// <i>Define number of cached Pages.
|
||||||
#define NAND1_SWECC 0
|
// <i>Default: 4 pages
|
||||||
|
#define NAND1_CAPG 4
|
||||||
// <o>File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
|
|
||||||
// <8=>8 KB <16=>16 KB <32=>32 KB
|
// <o>Block Indexing <0=>OFF <1=>1 block <2=>2 blocks <4=>4 blocks
|
||||||
// <i>Define System Cache buffer size for file IO.
|
// <8=>8 blocks <16=>16 blocks <32=>32 blocks
|
||||||
// <i>Increase this number for faster r/w access.
|
// <64=>64 blocks <128=>128 blocks <256=>256 blocks
|
||||||
// <i>Default: 4 kB
|
// <i>Define number of indexed Flash Blocks.
|
||||||
#define NAND1_CASZ 4
|
// <i>Increase this number for better performance.
|
||||||
|
// <i>Default: 16 blocks
|
||||||
// <e>Relocate Cache Buffers
|
#define NAND1_CABL 16
|
||||||
// <i>Use this option to locate Cache buffers
|
|
||||||
// <i>at specific address in RAM or SDRAM.
|
// <o>Software ECC <0=>None <1=>Hamming (SLC)
|
||||||
#define NAND1_RELOC 0
|
// <i>Enable software ECC calculation only,
|
||||||
|
// <i>if not supported by hardware.
|
||||||
// <o>Base address <0x0000-0xFFFFFE00:0x200>
|
#define NAND1_SWECC 0
|
||||||
// <i>Define base address for Cache Buffers.
|
|
||||||
#define NAND1_CADR 0x80000000
|
// <o>File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
|
||||||
|
// <8=>8 KB <16=>16 KB <32=>32 KB
|
||||||
// </e>
|
// <i>Define System Cache buffer size for file IO.
|
||||||
// <q>FAT Journal
|
// <i>Increase this number for faster r/w access.
|
||||||
// <i>Enable FAT Journal in order to guarantee
|
// <i>Default: 4 kB
|
||||||
// <i>fail-safe FAT file system operation.
|
#define NAND1_CASZ 4
|
||||||
#define NAND1_FSJ 0
|
|
||||||
|
// <e>Relocate Cache Buffers
|
||||||
// <q>Default Drive [N1:]
|
// <i>Use this option to locate Cache buffers
|
||||||
// <i>Used when Drive letter not specified
|
// <i>at specific address in RAM or SDRAM.
|
||||||
#define NAND1_DEF 0
|
#define NAND1_RELOC 0
|
||||||
|
|
||||||
// </e>
|
// <o>Base address <0x0000-0xFFFFFE00:0x200>
|
||||||
|
// <i>Define base address for Cache Buffers.
|
||||||
//------------- <<< end of configuration section >>> -----------------------
|
#define NAND1_CADR 0x80000000
|
||||||
|
|
||||||
#ifndef __NO_FILE_LIB_C
|
// </e>
|
||||||
#include <File_lib.c>
|
// <q>FAT Journal
|
||||||
#endif
|
// <i>Enable FAT Journal in order to guarantee
|
||||||
|
// <i>fail-safe FAT file system operation.
|
||||||
/*----------------------------------------------------------------------------
|
#define NAND1_FSJ 0
|
||||||
* end of file
|
|
||||||
*---------------------------------------------------------------------------*/
|
// <q>Default Drive [N1:]
|
||||||
|
// <i>Used when Drive letter not specified
|
||||||
|
#define NAND1_DEF 0
|
||||||
|
|
||||||
|
// </e>
|
||||||
|
|
||||||
|
//------------- <<< end of configuration section >>> -----------------------
|
||||||
|
|
||||||
|
#ifndef __NO_FILE_LIB_C
|
||||||
|
#include <File_lib.c>
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*----------------------------------------------------------------------------
|
||||||
|
* end of file
|
||||||
|
*---------------------------------------------------------------------------*/
|
||||||
|
|
|
||||||
|
|
@ -39,7 +39,7 @@
|
||||||
// <i> Set the stack size for tasks which is assigned by the system.
|
// <i> Set the stack size for tasks which is assigned by the system.
|
||||||
// <i> Default: 512
|
// <i> Default: 512
|
||||||
#ifndef OS_STKSIZE
|
#ifndef OS_STKSIZE
|
||||||
#define OS_STKSIZE 250
|
#define OS_STKSIZE 499
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
// <q>Check for the stack overflow
|
// <q>Check for the stack overflow
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -23,8 +23,6 @@
|
||||||
#include <config.h>
|
#include <config.h>
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#include <cyassl/ctaocrypt/settings.h>
|
|
||||||
|
|
||||||
/* on HPUX 11 you may need to install /dev/random see
|
/* on HPUX 11 you may need to install /dev/random see
|
||||||
http://h20293.www2.hp.com/portal/swdepot/displayProductInfo.do?productNumber=KRNG11I
|
http://h20293.www2.hp.com/portal/swdepot/displayProductInfo.do?productNumber=KRNG11I
|
||||||
|
|
||||||
|
|
@ -39,6 +37,7 @@
|
||||||
#ifdef NO_INLINE
|
#ifdef NO_INLINE
|
||||||
#include <cyassl/ctaocrypt/misc.h>
|
#include <cyassl/ctaocrypt/misc.h>
|
||||||
#else
|
#else
|
||||||
|
#define MISC_DUMM_FUNC misc_dummy_random
|
||||||
#include <ctaocrypt/src/misc.c>
|
#include <ctaocrypt/src/misc.c>
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
@ -60,7 +59,6 @@
|
||||||
#endif
|
#endif
|
||||||
#endif /* USE_WINDOWS_API */
|
#endif /* USE_WINDOWS_API */
|
||||||
|
|
||||||
#if !defined( NO_CYASSL_RANDOM )
|
|
||||||
|
|
||||||
#ifdef NO_RC4
|
#ifdef NO_RC4
|
||||||
|
|
||||||
|
|
@ -569,16 +567,20 @@ int GenerateSeed(OS_Seed* os, byte* output, word32 sz)
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
#elif defined(CYASSL_LPC43xx)
|
||||||
|
#warning "write a real random seed!!!!, just for testing now"
|
||||||
|
int GenerateSeed(OS_Seed* os, byte* output, word32 sz)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
for (i = 0; i < sz; i++ )
|
||||||
|
output[i] = i;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
#elif defined(NO_DEV_RANDOM)
|
#elif defined(NO_DEV_RANDOM)
|
||||||
|
|
||||||
#error "you need to write an os specific GenerateSeed() here"
|
#error "you need to write an os specific GenerateSeed() here"
|
||||||
/*
|
int GenerateSeed(OS_Seed* os, byte* output, word32 sz) { return(0) ; }
|
||||||
int GenerateSeed(OS_Seed* os, byte* output, word32 sz)
|
|
||||||
{
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#else /* !USE_WINDOWS_API && !THREADX && !MICRIUM && !NO_DEV_RANDOM */
|
#else /* !USE_WINDOWS_API && !THREADX && !MICRIUM && !NO_DEV_RANDOM */
|
||||||
|
|
||||||
|
|
@ -622,4 +624,3 @@ int GenerateSeed(OS_Seed* os, byte* output, word32 sz)
|
||||||
|
|
||||||
#endif /* USE_WINDOWS_API */
|
#endif /* USE_WINDOWS_API */
|
||||||
|
|
||||||
#endif /* NO_CYASSL_RANDOM */
|
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue