wolfBoot ships as source. Users build it in many ways. Before this
change, only the plain Make build could make an SBOM. So a user could not
make an SBOM for the build that the user runs.
This change adds one shared engine (tools/scripts/wolfboot-sbom.sh, which
calls wolfSSL gen-sbom) and a front end for each build system. Every
build makes a CycloneDX 1.6 and SPDX 2.3 document. The engine captures
the configuration with the host compiler, so the SBOM is the same for
GCC, Clang, LLVM, IAR, armcl, CCRX, and XC32.
Routes:
- Make, arch.mk, and vendor SDKs: make sbom TARGET=<t> SIGN=<a>
- CMake and the Pico SDK: cmake --build <dir> --target sbom
- IAR Embedded Workbench: ide-sbom/iar_sbom.py
- Any IDE with a compilation database: ide-sbom/compdb_sbom.py
- TI CCS, MPLAB X, Renesas, Xilinx: ide-sbom/route_through_sbom.sh
- Per-HAL component: make sbom-hal TARGET=<t>
- Zephyr module: ide-sbom/zephyr_sbom.py
Make the SBOM reproducible. The captured macros can hold an absolute host
path. For example, arch.mk passes -DPICO_SDK_PATH=$(PICO_SDK_PATH). The
driver now redacts each absolute path but keeps the macro name, so the
configuration record stays complete. Add --no-scrub for debug.
Add a validator (ide-sbom/validate_sbom.py) and a CI canary
(.github/workflows/test-sbom.yml) that runs and validates every route.
The canary also checks that no host path leaks into the SBOM.
Add docs/SBOM.md. The tools are product-neutral by design, so they can be
shared across wolfSSL products later without logic changes.
Signed-off-by: Sameeh Jubran <sameeh@wolfssl.com>
Run wolfBoot on the PIC32CZ CA9x host core (Cortex-M7) as a wolfHSM client,
offloading the image digest (SHA-256) and the ECDSA P-256 signature check to
the wolfHSM server.
- Document wolfBoot_erase_partition() lock postcondition in doxygen
- Comment the hwswap anti-rollback guard as defense-in-depth
- Clarify sim-dualbank-rollback-denied.sh purpose via header comment
- Simplify lock guards in unit-nvm partition_magic_write test
hal/nrf52.c:
- Use static volatile buffer for UARTE DMA source instead of stack
variable address. GCC 15.2 with -Os optimized away the store to the
stack slot, causing the DMA to read zeros.
- Set UART0_ENABLE to 4 (UARTE mode) per NRF52840 datasheet.
tools/test-expect-version/test-expect-version.c:
- Replace deprecated termio.h and linux/serial.h with sys/ioctl.h
for compatibility with newer glibc.
tools/renode/docker-test.sh:
- Remove unused RENODE_CHECKOUT env var.
tools/scripts/renode-test-update.sh:
- Add robust UART wait functions with timeouts and liveness checks.
- Log Renode output to /tmp/renode.log for diagnostics on failure.
- Use run_expect_version helper with configurable timeout.
hal/zynq.c:
- Route IOU_TAPDLY_BYPASS writes through pmu_request at EL<=2 in the
<=40 MHz and <=100 MHz branches (previously only done at <=150 MHz);
the register is equally unwritable from EL2/EL1 at lower clocks.
- Add qspi_flash_reset() (RESET_ENABLE 0x66 + RESET_MEMORY 0x99),
called per chip in qspi_init so the flash starts from a known state
regardless of what FSBL/BootROM left behind (XIP, 4-byte addr,
auto-boot).
- Drop unused 'reg' in csu_aes and 'ms' in csu_init so
-Werror=unused-variable builds (OPTIMIZATION_LEVEL=0 / DEBUG=1) pass.
hal/zynq.ld:
- Move wolfBoot ORIGIN from 0x08000000 to 0x10000000. Large FIT images
(kernel load=0x00200000, payload >~126 MB) would sweep across
0x08000000 at handoff and overwrite wolfBoot's own code.
tools/scripts/zcu102/zcu102-ca53-qspi.cmm:
- Rewrite against the Lauterbach TRACE32 ZCU102 QSPI demo: PREPAREONLY
entry mode, single/dual toggle, READ_ID_TEST, separate flash dialogs
for BOOT.BIN (offset 0) and test-app/image_v1_signed.bin.
- Document the ~128 MB TRACE32 temp-memory ceiling on FLASHFILE.Create:
larger files must be split externally and loaded in chunks.
- HAL: Remove debug spifi_test_mode_switch(), use wolfBoot_printf
instead of raw uart_write, add printf.h include
- Test app: Use check_parts() (was defined but unused), replace
custom print_str/print_hex32 with wolfBoot_printf, fix LED logic
to show LED1 for v1 and LED2 for v2+ (was always LED1)
- Docs: Remove incorrect MCUXpresso SDK section (port is bare-metal),
fix typo, add swap timing note, add flash script references
- Build: Add --no-warn-rwx-segments to arch.mk, improve Makefile
comments
- Add tools/scripts/nxp-lpc54s018m-flash.sh following the
nxp-s32k142-flash.sh pattern (build, sign, flash via pyocd)
Tested: full boot + firmware update cycle (v1 -> v2 swap) verified
on LPC54S018M-EVK hardware.
Adds support for running wolfBoot in **Machine Mode (M-mode)** on the PolarFire SoC MPFS250T, booting from eNVM and loading a signed application from **SC QSPI flash** into on-chip LIM (Loosely Integrated Memory). No HSS (Hart Software Services) or DDR is required. It also extends the existing PolarFire HAL with multi-hart support, L2 cache configuration, per-hart UART, and refactors shared code (SDHCI, SCB mailbox, linker/test-app) for both S-mode and M-mode builds.
David Garske
Brett Nicholas
Sameeh Jubran
Marco Oliverio
Daniele Lacamera
Thomas Cook
Aidan Garske