Commit Graph

25 Commits (42e6dba558a27e3162b5b0bf5a4dd24075923b68)

Author SHA1 Message Date
Daniele Lacamera 42e6dba558 pkcs11 store: invalidate the flash read cache after every commit
The store commits sectors with hal_flash_erase()/hal_flash_write() and
then reads them back through the memory map - sector_ptr(),
cache_get_sector()'s refill, and the raw magic reads in check_vault().
On a part that caches flash reads (STM32 ICACHE) those reads can return
pre-erase bytes. check_vault() is the worst case: a stale magic there
does not merely read wrong, it triggers restore_backup() or a full vault
re-initialisation, losing the token.
2026-09-10 10:45:55 +02:00
Daniele Lacamera cfd44bc5c1 F-12878: STM32U5: program the 16-byte unit through an aligned pointer
An unaligned starting address split the four word stores across two
16-byte program units, leaving partial quad-words that set
FLASH_SR_WDW and hang the wait for completion. Align the destination
down to the unit, read-modify-write the whole unit, and store through
the aligned pointer. The unit test gains unaligned-start cases.
2026-09-07 16:31:07 +02:00
Daniele Lacamera 57db8948d1 Remove tracker ids from code, condense comments
Drop the internal report numbers from source, test and Makefile
comments: they mean nothing outside the tracker and do not belong in
the tree. Condense the long inline comment blocks the review flagged,
and note in the raspi3 encrypted example and its docs that CI builds
but does not boot it, so the end-to-end path has no automated
coverage.

Comments and docs only; no functional change.
2026-08-18 19:48:12 +02:00
Daniele Lacamera 78ba84cc23 stm32l5/u5: program the whole flash unit in one PG window
The partial-tail handling skipped the words that hold no requested
byte. Neither part can do that: U5 only starts the 128-bit program on
the fourth word (a partial quad-word leaves FLASH_SR_WDW set and
hal_flash_wait_complete() never returns), and L5 has no 32-bit program
mode, so splitting the double word into two PG cycles programs
nothing and faults the second on alignment.

Build the full unit first, taking bytes outside [i, len) from the
current flash content as hal/stm32h5.c does, then store every word.
That drops the over-read F-9763/F-9764 targeted without ever issuing
a partial unit. L5 TZ claim widened to the 8-byte boundary to match.
2026-08-18 08:41:26 +02:00
Daniele Lacamera 263d3d5fbf F-9764: keep STM32U5 hal_flash_write within the requested length
hal_flash_write() looped while (i < len) but programmed whole 16-byte
units: each iteration read all four 32-bit source words unconditionally
and wrote the full quadword to flash, so a write whose length is not a
multiple of 16 read up to 12 bytes past the caller's buffer - which
the NSC update path validates for exactly len - and wrote those bytes
to flash.

Program the unit word by word: each word is written only when at least
one of its bytes is requested, and a partial final word is padded with
the erased value (0xFF) in its upper bytes so no source bytes past len
are read. The single PG/wait/clear sequence per unit is unchanged.

Test: tools/unit-tests/unit-stm32u5-write.c is the 16-byte twin of the
STM32L5 test (F-9763): it extracts the real hal_flash_write() and its
wait/clear helpers, maps the destination flash at a 32-bit host address
(the parameter is uint32_t on this 32-bit target) pre-filled with stale
data, and runs short writes; pre-fix the bytes past len landed in the
destination flash in all four partial-unit cases.
2026-08-18 05:52:08 +02:00
Mattia Moffa 6b8702dd63 Add uart driver for stm32u5 2026-07-31 16:00:14 +02:00
Daniele Lacamera 7baf9e65f7 stm32u5: fix erase bank selection when SWAP_BANK is active
On STM32U5 the BKER bit in FLASH_NSCR/SECCR always selects the
physical bank: the SWAP_BANK option only changes the address mapping
of the banks (RM0456 7.5.8, and confirmed on silicon). hal_flash_erase
derived BKER from the logical address only, so with SWAP_BANK active
every page erase landed in the bank opposite to the one mapped at the
target address.

In DUALBANK_SWAP mode this broke fallback recovery: when image
verification failed while running from bank 2, wolfBoot_erase_partition
(PART_UPDATE) erased the healthy image in the active bank instead of
the failing update, leaving the device unable to boot. The same
mismatch corrupted any erase issued while swapped, including staging a
new update from the application.

Invert BKER when both DBANK and SWAP_BANK are set, mirroring the
STM32H5 HAL which already handles this (RM0481 has the same physical
bank semantics). STM32L5 is not affected: RM0438 defines NSBKER as the
page number MSB, which follows the mapped address.

Verified on the m33mu emulator with hardware-faithful BKER/SWAP_BANK
modeling: full cycle (update to bank 2, swap, stage corrupt update,
verify failure) now erases the corrupt update and falls back to the
healthy image; before this fix the healthy image was erased and the
device bricked.
2026-07-09 12:09:14 +02:00
Mattia Moffa f2b95c2563 STM32H5, STM32U5, STM32L5: fix off-by-one error in hal_flash_erase
F#3537
2026-05-06 19:03:12 +02:00
Daniele Lacamera 776378ca78 Preparing release v2.8.0 + update copyright 2026-04-16 13:11:56 +02:00
Daniele Lacamera f94d9d2ed1 fix option unlock wait condition
F/723
2026-03-16 09:18:57 +01:00
Daniele Lacamera 9e7f6c24ec Fixes after reviewer's comment
- Fix misnamed STM32U585 register
- Remove emu-test-apps linker scripts as they are autogenerated
2026-01-19 12:37:37 +01:00
Daniele Lacamera 97b6f3b63b Fixes for stm32u5, added workflow test 2026-01-15 13:54:10 +01:00
David Garske 2546ebcaf9 Fixes for unused variables. Also repaired STM32WB55 build with PKA 2025-11-20 18:26:58 +01:00
Mattia Moffa d5b2b4728d Various STM32 TrustZone improvements
- New config flags for flash geometry
- New script to automatically set option bytes
- End of stack address fix for the STM32U5 test app
- STM32U5 support for NUCLEO-U575ZI-Q (previously only supported
  discovery board)
2025-11-20 18:00:55 +01:00
David Garske ecf1cb8a92 Peer review fixes. Added new WOLFBOOT_RESTORE_CLOCK option 2025-11-19 11:11:28 +01:00
gojimmypi fbd8dcf8a2
Update Copyright year to 2025 2025-10-15 11:33:53 -07:00
David Garske 1967cc2670 STM32U5: Only try and invalidate cache if enabled. 2024-06-25 21:57:54 +02:00
David Garske a92c1b9ad9 STM32U5 cache support. Including cache invalidate on `nvm_select_fresh_sector`. ZD 18210 2024-06-25 18:12:47 +02:00
Daniele Lacamera 19fdbb8998 Initial support for STM32H5, sunny day boot
STM32H5: Tested sunny day boot

- Temporarily decreased clock speed to 125MHz
- Test app working
- Re-mapped Nucleo board LEDs
- Tested on STM32H563ZI
2024-05-09 16:28:06 +02:00
Daniele Lacamera fce6149cf8 Update license GPL2 -> GPL3 2024-04-16 16:46:15 +02:00
Daniele Lacamera c25497eba9 DUALBANK: fork_bootloader should only execute once
fork_bootloader() should perform a physical copy of
the bootloader to its partition in the second bank only
if the content of the two partitions does not already match.
2024-02-15 16:55:33 +01:00
Daniele Lacamera b5c8bc8024 Fix cppcheck warnings 2023-10-13 15:49:12 +02:00
Daniele Lacamera e2ab9a5553 Unified TZ support for STM32L5/U5
- added file with common code
- added support for TRNG on U5
- added support for wolfcrypt NSC on U5
2023-09-21 07:57:18 +02:00
Dimitri Papadopoulos be037ca04d Fix typos found by codespell 2023-07-04 07:43:02 +02:00
David Garske 5463105eab Adds STM32U5 support. Thank you ST. 2022-01-24 00:07:03 -08:00