WolfSSL
/
wolfBoot
mirror of https://github.com/wolfSSL/wolfBoot.git
1
0
Fork 0
Code Issues Releases Wiki Activity
4,111 Commits
31 Branches
33 Tags
60 MiB
Commit Graph

515 Commits (master)

Author SHA1 Message Date
Thomas Cook 13d11a85bc Misc cleanup 2026-11-04 20:24:54 +01:00
Thomas Cook fcbde929d8 TI AM64x port, based on the TI MCU Plus SDK 11.02, running on one of the cortex-r5f's. 2026-11-04 20:24:54 +01:00
David Garske 767ef3de3c Add compressed firmware updates installed into an execute-in-place slot 2026-11-04 14:35:53 +01:00
Mattia Moffa 6d79499e45
Merge pull request #962 from dgarske/mpfs250_emmc_qspi 
Add PolarFire SoC support for M-Mode (HSS replacement) booting from eMMC and QSPI into DDR
 2026-10-29 19:04:07 +01:00
Yosuke Shimizu 6432acc612 Add RX71M clock, UART, LED and code flash driver 
- hal_clk_init(): rx71m runs the main crystal (RX_MAIN_XTAL_HZ,
  default 24MHz) through the PLL to 240MHz.
- hal_prepare_boot(): under WOLFBOOT_RESTORE_CLOCK, switch to the
  LOCO and stop the PLL and main oscillator on rx71m.
- uart_init(): SCI7 on P90/P92 by default; uart_write() waits for
  TEND. hal_led_on()/hal_led_off(): LED0 on P03.
- renesas-rx.c: TARGET_rx71m flash driver run from RAM, with #error
  unless RAM_CODE and __WOLFBOOT are defined. It copies the FCU
  firmware at init, programs 256-byte units at most once per erase,
  and masks interrupts with timeouts and FSTATR checks for each
  program and erase.
- renesas-rx.h: PSW, FASTAT and FAEINT bits and the new flash
  error codes.
- renesas-rx71m.config: commented RX_MAIN_XTAL_HZ line.
- test-app: link .ramcode into RAM and build renesas-rx.o with
  RAM_CODE and __WOLFBOOT for rx71m.
 2026-10-29 07:01:54 +01:00
Yosuke Shimizu ddb4085dcf Add RX71M target build wiring and boot tables 
- renesas-rx71m.config, rx71m.ld, rx71m.c: RSK+ RX71M layout with
  NVM_FLASH_WRITEONCE=1, .romcode at 0xFFFFFF80 and .ofs_rx71m at
  0x00120040.
- arch.mk: reject PKA, DELTA_UPDATES and NVM_FLASH_WRITEONCE other
  than 1 for rx71m; build with -misa=v2; drop .ofs_rx71m from
  wolfboot.bin and fill gaps with 0xFF.
- renesas-rx.h: rx71m clock, flash, FACI and MPC values;
  hal_clk_init() sets SYS_MEMWAIT.
- boot_renesas.c: INT_Fault for the rx71m fault vectors,
  RomCodeArea[] with ROMCODE 0xFFFFFFFF, and the option-setting
  array under WOLFBOOT_RENESAS_OSM.
 2026-10-29 07:01:54 +01:00
David Garske 29b5476ead PolarFire SoC: boot the HSS replacement from eMMC and QSPI into DDR 2026-10-28 21:06:08 -07:00
Mattia Moffa 24776f3b7a
Merge pull request #949 from dgarske/psoc_e8 
Add wolfBoot target for Infineon PSOC Edge E8
 2026-10-28 23:02:17 +01:00
David Garske eca987ba9d
Merge pull request #952 from danielinux/signer-claimed-role-fix 
boot: bind image partition claim to the booting core
 2026-10-28 14:35:37 -07:00
David Garske 3681ea8996 Add wolfBoot target for Infineon PSOC Edge E8 2026-10-28 14:24:42 -07:00
twcook86 aa9685b03a
Merge pull request #950 from aidangarske/lpc55s69-port-update 
Harden LPC55S69 TrustZone isolation and add tests, CI and docs
 2026-10-28 15:12:27 -04:00
Daniele Lacamera 720eaf4564 sim monolithic self-update: sign the stripped test app 2026-10-28 14:48:44 +01:00
Daniele Lacamera 76a8b2b3ea Refuse partitions too small for the trailer, add STM32F4 custom trailer (#937) 2026-10-28 14:35:31 +01:00
Aidan Garske 3345f87fba Harden LPC55S69 TrustZone isolation and add tests, CI and docs 2026-10-27 16:15:37 -07:00
David Garske 47e8f57dcb PolarFire SoC: correct the FIT staging address rationale in the M-mode config 2026-10-27 16:06:05 -07:00
David Garske 58ba1038ec PolarFire SoC: correct the MSS watchdog and reset-cause register semantics 2026-10-27 16:06:05 -07:00
David Garske 84e4e16328 PolarFire SoC: consolidate the documentation into docs/PolarFire.md with a quick start 2026-10-27 16:06:05 -07:00
David Garske b4e2436040 PolarFire SoC: boot mode 2 User Boot Loader stub verifying the eNVM wolfBoot 2026-10-27 16:06:05 -07:00
David Garske 6778bf3bb2 PolarFire SoC: read DDR once after init so CPU writes land, drop the workarounds 2026-10-27 16:06:05 -07:00
David Garske a91c824e45 PolarFire SoC: sNVM/PUF key storage and disk image encryption 2026-10-27 16:06:04 -07:00
David Garske 0e2e7e7e31 PolarFire SoC: M-mode scratchpad, DDR training, SBI and CI fixes 2026-10-27 16:06:04 -07:00
Brett Nicholas 41fbe4b326 Improve support for ECC flash parts: 
- Add NVM ECC mode, which introduces a new erase check HAL API to use
   flash controller HW to blank check sectors instead of reading them
   and comparing to an erased byte (which typically triggers an ECC
   fault)
 - Add NVM Journal mode as an alternative to NVM_FLASH_WRITE_ONCE that
   does not require a sector-size RAM buffer and dramatically reduces
   the number of erases and programs required to set individual flags,
   while also being much more robust to power-cuts.
 2026-10-27 16:46:40 +01:00
David Garske b555895193
Merge pull request #948 from aidangarske/mcxn-secure-app 
Add an MCXN947 secure application handoff config
 2026-10-26 16:07:49 -07:00
Aidan Garske 051a2a47ac
Merge pull request #787 from twcook86/lpc55s69_hwpuf 
Support for PUF in LPC55S69
 2026-10-26 08:28:51 -07:00
Marco Oliverio b240ee7aaa
Merge pull request #933 from dgarske/nai_68int6 
Add wolfBoot target for the NAI 68INT6 (Intel Tiger Lake UP3) OpenVPX SBC
 2026-10-26 10:04:12 +01:00
David Garske d490e36d2e fdt: boot a FIT with no kernel load/entry and no device tree 2026-10-23 11:49:49 -07:00
Aidan Garske 1d47fa7b62 Add an MCXN947 secure application handoff config with m33mu tests 2026-10-23 18:27:33 +01:00
Thomas Cook 38d7655080 address pr comments 2026-10-22 17:36:22 -04:00
David Garske aef57a113d versal: support the system watchdog timer (WWDT) 2026-10-22 18:11:12 +02:00
Thomas Cook 85d056dad7 update configs 2026-10-20 10:36:26 +02:00
Thomas Cook 2dc0488d08 Update docs, tweak configs 2026-10-20 10:36:26 +02:00
Thomas Cook 8fb226dd48 Add psa attestation support for lpc55s69 2026-10-20 10:36:26 +02:00
Thomas Cook 057ea0ef78 default HWPUF off 2026-10-20 10:36:26 +02:00
Thomas Cook b65752a538 Initial implementation 2026-10-20 10:36:26 +02:00
David Garske 4304085f32
Merge pull request #945 from bigbrett/pss-default 
quickfix: TC3 example config change
 2026-10-19 14:19:32 -07:00
Brett Nicholas 0d1952a517 change AURIX RSA configs to use PSS 2026-10-19 14:53:12 -06:00
David Garske 608610dc16 imx95_a55: add the Cortex-A55 target and a stage 1 replacing U-Boot SPL 2026-10-15 15:27:28 -07:00
Aidan Garske 1b425abfe8 Add Agilex 5 FCS and wolfBoot integration 2026-10-15 10:25:33 -07:00
David Garske 363483ed54 nai_68int6: add wolfBoot target for the NAI 68INT6 (Intel Tiger Lake UP3) OpenVPX SBC 2026-10-14 21:56:32 -07:00
David Garske aa6fdb8fa9 x86 FSP: add TPM-NV anti-rollback with a persistent version floor and boot audit counters 2026-10-14 21:56:32 -07:00
Mattia Moffa 400bce6317
Merge pull request #924 from dgarske/stm32h7s 
Add wolfBoot target for STM32H7S3L8 with partitions on external Octo-SPI NOR
 2026-10-12 20:40:19 +02:00
David Garske e415826eb7 Add STM32H7S target with partitions on external Octo-SPI NOR 2026-10-11 21:45:53 -07:00
David Garske 1f6f27cb4b
Merge pull request #930 from aidangarske/nrf54lm20-port 
Add nRF54LM20 support and fix nRF54L RAM code, keyvault, and cache
 2026-10-11 21:29:37 -07:00
Aidan Garske e493aee67f Harden the NXP MCX W71 port and add console, timer and wolfCrypt-TZ 2026-10-09 21:04:57 +01:00
David Garske 79fe3e694e
Merge pull request #926 from aidangarske/rw612 
Add NXP FRDM-RW612 port and test NXP HALs against the real MCUXpresso SDK
 2026-10-09 12:26:07 -07:00
Aidan Garske d147db6dfd Add NXP RW612 target with TrustZone support 2026-10-09 17:06:01 +01:00
Aidan Garske 7abadf1ae0 Add nRF54LM20 support to the nRF54L port 2026-10-07 22:52:28 +01:00
David Garske 508ad6a26d Add wolfBoot target for Infineon PSOC Control C3 2026-10-06 18:14:10 +02:00
David Garske 7b71f28aa3 versal: support DDR apertures above 1 TB in the translation table 2026-09-24 13:13:33 +02:00
Aidan Garske 35f9c0964f Align the i.MX RT700 ML-DSA image header to its 16 KB sector 2026-09-24 13:12:36 +02:00