Commit Graph

216 Commits (6d652d444fe150090f18b592e673d4f217728bc3)

Author SHA1 Message Date
Brett Nicholas 6d652d444f Support for AURIX TC4xx host and CSRM cores 2026-09-12 09:21:38 -06:00
David Garske bafa907e9a
Merge pull request #873 from danielinux/pkcs11-store-batch-commit
pkcs11 store: Improve Store performance through batch sector commits to Store_Close
2026-09-10 16:14:04 -07:00
Brett Nicholas 678781db39 AURIX tc3 ARCH/TARGET refactor anticipating TC4xx 2026-09-10 10:19:08 -06:00
Daniele Lacamera febf29ad61 pkcs11 store: batch sector commits to Store_Close
Every wolfPKCS11 field write flushed the payload sector and the header
sector to flash (2 erases + 2 programs of a full sector each), and the
token store re-serializes all objects per C_CreateObject/C_DestroyObject,
so those calls cost hundreds of sector erases and tens of seconds on
flash with slow erase times.

Cache modified sectors in RAM and commit them together when the store
window closes:

- sector cache sized to the worst-case span of one object plus the
  header sector (WOLFBOOT_PKCS11_STORE_CACHE_SECTORS), LRU eviction
  when exceeded
- header sector commits last, so a committed header is the atomic
  commit point of the batch: power failure during a flush leaves the
  flash in either the pre-batch or the post-batch state
- per-commit backup sector write preserved, keeping recovery of the
  sector in flight at failure time
- delete_object commits on return (durability contract, unit-tested)
- nodes table, bitmap, payload ids and the live object size
  (handle->size) are read from the cache when the sector is dirty

Measured on an STM32H5 with 8KB sectors, wolfPKCS11 in the secure
world: C_CreateObject 1.5s -> 0.15s, C_DestroyObject 1.3s -> 0.12s,
456 -> 40 sector erases per create, and the count no longer scales
with the number of objects in the token.

PKCS11_STORE_STATS (off by default) adds flash-activity counters and a
test-app bench to quantify store traffic: make PKCS11_STORE_STATS=1.
2026-09-10 09:40:02 +02:00
David Garske 4fedc93ed8 imx95_m7: fix console/status overlap, cache handoff, timebase and build wiring 2026-08-24 18:46:41 +02:00
David Garske 724ca34677 Add wolfBoot target for NXP i.MX95 Cortex-M7 2026-08-24 18:46:41 +02:00
David Garske 88984858d5 Peer review fixes (thanks Jack) 2026-08-24 12:47:34 +02:00
David Garske 485b446e9e
Merge pull request #848 from bigbrett/tc3-fix-uart-gates
tc3: fix debug uart macro protection
2026-08-10 12:31:31 -07:00
Brett Nicholas 5eaf0b0a55 tc3: fix debug uart macro protection 2026-08-10 10:38:49 -06:00
David Garske 64a6ef420d test-app: run wolfCrypt test/benchmark on PolarFire SoC MPFS250 2026-08-03 12:27:22 +02:00
Mattia Moffa 6da07ffc3d Add support for ARM Compiler for Embedded on stm32u5 2026-07-31 16:00:14 +02:00
Mattia Moffa 6b8702dd63 Add uart driver for stm32u5 2026-07-31 16:00:14 +02:00
Mattia Moffa 459ec8a7d6 Fix warnings for test-app crypto test 2026-07-31 14:33:56 +02:00
Mattia Moffa 357734d691 Fixes for old Maxim SDK 2026-07-31 14:33:56 +02:00
Mattia Moffa 190de90224 Clean up build flag usage, use trng healthtest in test-app 2026-07-31 14:33:56 +02:00
Mattia Moffa 60b9e87413 SHA256 acceleration for bootloader 2026-07-31 14:33:56 +02:00
Mattia Moffa f5f54c294e Implementation of test-app crypto test 2026-07-31 14:33:56 +02:00
David Garske eaa39be9e4 renesas-rx: fix build for GCC RX 8.3/14.2 2026-07-30 15:32:31 +02:00
David Garske 29c9ea1ce1 test-app: add wolfIP + wolfCrypt test harness and PPC crypto asm 2026-07-30 13:29:09 +02:00
Marco Oliverio 36b665bfcc pic32cz: add wolfHSM client target
Run wolfBoot on the PIC32CZ CA9x host core (Cortex-M7) as a wolfHSM client,
offloading the image digest (SHA-256) and the ECDSA P-256 signature check to
the wolfHSM server.
2026-07-29 18:07:45 +02:00
aidan garske b9bd6dae17 Add WOLFCRYPT_TZ_WOLFHSM TrustZone engine for STM32H5 2026-06-24 15:49:43 -07:00
Alex Lanzano 01c52d87e8 remove wolfhal TARGET. Add WOLFHAL option 2026-06-10 17:12:25 +02:00
Alex Lanzano 125872c571 Create STM32WB wolfHAL example. GC sections on all test apps 2026-06-10 17:12:25 +02:00
David Garske c075549ea2 Add wolfBoot support for STM32G4 2026-05-29 13:10:15 +02:00
David Garske 9786f5608b Add wolfBoot port for STM32N6 (NUCLEO-N657X0-Q)
Co-authored-by: Aidan Garske <aidan@wolfssl.com>
2026-05-28 16:49:57 +02:00
Alex Lanzano a41a98551b Fix mcxn build by providing the RNG for TZ_PSA builds 2026-05-26 17:13:17 +02:00
Tobias Frauenschläger cab04ad789 Update wolfssl submodule to latest master
* file level rename for ML-DSA
* Add missing source file to build system
* Update some macros
* Other minor fixes
* Update size limitations for some slight increases
2026-05-18 23:02:54 -07:00
David Garske b94954eab4 Add Xilinx Zynq-7000 (ZC702) wolfBoot port 2026-05-12 12:06:05 +02:00
Thomas Cook 6093b68f15 Fix lingering lpc55s69 issues 2026-05-07 17:06:35 -04:00
Mattia Moffa fda8668cc3 Address Copilot comments 2026-05-07 21:39:34 +02:00
Mattia Moffa dc6cfaaf83 Kinetis KL26 port 2026-05-07 21:39:34 +02:00
David Garske af40ae1471 Add STM32C5 target (NUCLEO-C5A3ZG) 2026-05-06 19:02:58 +02:00
Brett Nicholas 149db43612 tc3: add echo test to test-app when wolfHSM is enabled 2026-05-05 16:37:54 +02:00
Thomas Cook 2eeffd68e1 address pr issue 2026-04-27 17:30:42 +02:00
Thomas Cook d2ef348763 Rework rng a bit 2026-04-27 17:30:42 +02:00
Thomas Cook b545979da0 address several pr issues 2026-04-27 17:30:42 +02:00
Thomas Cook 8d3f459d20 Regression test fixes 2026-04-27 17:30:42 +02:00
Thomas Cook e83f61c9db Add benchmark and test capability to test-app 2026-04-27 17:30:42 +02:00
Thomas Cook 8c6d6e2fc6 Better hook rng into wolfCrypt 2026-04-27 17:30:42 +02:00
David Garske 980022de13 Add wolfBoot port for STM32U3 (NUCLEO-U385RG-Q)
New HAL port for the STM32U3 family (Cortex-M33, no TrustZone,
1MB dual-bank flash with 4KB pages, 64-bit double-word writes).

Features:
- hal/stm32u3.c, hal/stm32u3.h, hal/stm32u3.ld: flash driver,
  clock init (96 MHz MSIRC0 via EPOD booster), inline UART, ICACHE
- config/examples/stm32u3.config: ECC384/SHA384, DEBUG_UART=1,
  NVM_FLASH_WRITEONCE=1, RAM_CODE=1, dual-bank layout
- test-app/app_stm32u3.c: LED blink + UART output + version check
- tools/scripts/prepare_update_u3.sh: v2 pBOOT update image builder
- docs/Targets.md: STM32U3 section with build/flash/update instructions
- CI: stm32u3_test job + Clang rebuild coverage

Tested on NUCLEO-U385RG-Q:
- Verified boot with ECC384/SHA384 signature
- 96 MHz clock (MSIRC0 + SMPS + EPOD booster + VOS1)
- UART output on USART1 PA9/PA10 (ST-LINK VCP)
- TEST_FLASH erase/write/readback on both flash banks
- A/B firmware update (v1 -> v2 swap with pBOOT trigger)
2026-04-27 17:00:41 +02:00
David Garske 8b7ce4e4dd
Merge pull request #756 from danielinux/fTPM-TZ
Added support for fwTPM in TrustZone + STM32H5 test app
2026-04-22 14:10:19 -07:00
Daniele Lacamera cffa75d4a4 Proper interface renaming + documentation 2026-04-22 14:14:28 +02:00
David Garske 00313b3e43 Rename LPC54S018M to LPC54S0XX 2026-04-22 14:10:55 +02:00
David Garske 46deb232ff Fixes for clocks and testing updates. 2026-04-22 14:10:55 +02:00
Aidan Garske 9673509c04 Clean up NXP LPC54S018M port and align with LPC55S69 patterns
- HAL: Remove debug spifi_test_mode_switch(), use wolfBoot_printf
    instead of raw uart_write, add printf.h include
  - Test app: Use check_parts() (was defined but unused), replace
    custom print_str/print_hex32 with wolfBoot_printf, fix LED logic
    to show LED1 for v1 and LED2 for v2+ (was always LED1)
  - Docs: Remove incorrect MCUXpresso SDK section (port is bare-metal),
    fix typo, add swap timing note, add flash script references
  - Build: Add --no-warn-rwx-segments to arch.mk, improve Makefile
    comments
  - Add tools/scripts/nxp-lpc54s018m-flash.sh following the
    nxp-s32k142-flash.sh pattern (build, sign, flash via pyocd)

  Tested: full boot + firmware update cycle (v1 -> v2 swap) verified
  on LPC54S018M-EVK hardware.
2026-04-22 14:10:55 +02:00
Aidan Garske 943d4fd866 Fix NXP LPC54S018M SPIFI flash operations and complete boot+update cycle
The LPC54S018M HAL had three critical SPIFI controller issues preventing
   flash write/erase operations from working, which blocked wolfBoot_success(),
   wolfBoot_update_trigger(), and the firmware swap:

   1. Wrong memory-mode read command: Used opcode 0x6B (Quad Output, serial
      address) but the boot ROM configures 0xEB (Quad I/O, quad address) with
      MCMD=0xEB930000. The mismatch caused garbled address bits when re-entering
      XIP after flash operations, crashing on instruction fetch.

   2. SPIFI POLL mode not waiting: The boot ROM leaves CLIMIT[7:0]=0x00 which
      makes the hardware POLL comparison always succeed immediately. Set
      IDATA=0x00 and CLIMIT[7:0]=0x01 to properly wait for flash BUSY to clear.

   3. SPIFI reset clears CTRL/CLIMIT: The reset used to exit memory mode clears
      the boot ROM's timing config (CTRL=0x600F03E8) and cache limit
      (CLIMIT=0x08000000). Save and restore both registers around every reset.

   Additional changes:
   - Add RAMFUNCTION memcpy (src/string.o) to test app for SPIFI XIP safety
   - Add bare-metal UART driver for Flexcomm0 (non-blocking, skips if FC0
     doesn't respond — observed on some LPC54S018M-EVK boards)
   - Add DSB+ISB barriers after entering memory mode for pipeline coherency
   - Enable DEBUG_UART in example config
   - Update test app to follow LPC55S69 port patterns with LED indicators
     for boot version and update status

   Tested: cold boot, ECC256 signature verify, wolfBoot_success(),
   wolfBoot_update_trigger(), and full v1->v2 firmware swap all working.
   Swap takes ~60 seconds for the 960KB partition (240 sector operations).
2026-04-22 14:10:55 +02:00
David Garske 91145d53bb Add wolfBoot support for NXP LPC54S018M-EVK 2026-04-22 14:10:55 +02:00
Daniele Lacamera b22c85ed27 Added support for fTPM in TrustZone + STM32H5 test app 2026-04-21 20:53:48 +02:00
David Garske 58c2e044a6
Merge pull request #730 from danielinux/clang-linker
Fix embedded images built with the clang compiler
2026-04-13 10:55:19 -07:00
Daniele Lacamera 201c2c5c7e Adjust BIGINT limits for new wolfSSL ECC+SMALLSTACK 2026-04-07 14:14:44 +02:00