WolfSSL
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wolfBoot
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32 Commits (fce6149cf8df011484da689d064ef1909e18cddc)

Author SHA1 Message Date
Daniele Lacamera fce6149cf8 Update license GPL2 -> GPL3 2024-04-16 16:46:15 +02:00
Daniele Lacamera dcb82b6545 cppcheck: added "--enable=warning" 2023-10-13 16:08:22 +02:00
David Garske 0f4675f6b7 Fixes and improvements for NXP QorIQ: 
* Fix and refactor the L2SRAM support and use it for stage 1 loader stack.
* Fix NXP eSPI driver to support all sizes and properly handle keeping CS active.
 2023-08-04 16:31:09 +02:00
David Garske 4e93027cb9 Fix execute bit 2023-05-10 16:55:01 -07:00
David Garske 28ee143a1b Update the new `spi_xfer` to include a "continue" flag to allow leaving the CS asserted. 2023-05-10 15:26:57 -07:00
David Garske 0f110e4cd9 Progress on eSPI support for NXP P1021 TPM. 2023-05-04 15:23:45 -07:00
David Garske 8dd0ee347f Support for the STM32 OCTOSPI peripheral. 2023-02-02 12:11:23 -08:00
Daniele Lacamera 74a26d20c8 Fixed regressions on TPM SPI communication 
that were introduced in #265
 2022-12-29 16:11:34 +01:00
David Garske e746c3f65a Fix for wolfBoot with wolfTPM. Tested with `cp ./config/examples/stm32wb-tpm.config .config && make clean && make`. 2022-12-28 19:15:50 +01:00
David Garske a93eacf510 Improve QSPI driver performance. 2022-12-22 15:29:24 -08:00
David Garske 8d7d4d4f74 Fixes for QSPI read. Adds alternate byte support. Cleanup of simple QSPI read/write. 2022-12-22 15:02:31 -08:00
David Garske c3cf21a81f STM32 QSPI cleanups. 2022-12-21 14:06:31 -08:00
David Garske 5331f5ee23 QSPI Flash tests passing in single SPI mode (working on Quad mode). 
```
wolfBoot Init
Flash ID (ret 0): 0x1870EF, status 0
Erase Sector: Ret 0
Flash Write: Ret 0, Address 0x200000, Page 0, Len 256
Write Page: Ret 0
Flash Read: Ret 0, Address 0x200000, Len 256, Cmd 0xB
Read Page: Ret 0
Checking...
Flash Test Passed
```
 2022-12-20 16:44:53 -08:00
David Garske 26bed3e893 Fixes for QSPI driver (CS is controller by QSPI). Fix little endian byte ordering for UART printf feature. 2022-12-20 15:00:26 -08:00
Daniele Lacamera bf62ebe3fd Fix GPIO mode for SPI CS pins 2022-12-20 13:54:17 +01:00
David Garske 1766864a6b Fixes for STM32 QSPI and cleanups. Added build-option for QSPI clock (`QSPI_CLOCK_MHZ`). 2022-12-20 13:31:28 +01:00
David Garske a9526bab8f STM32 QSPI Flash support. Refactor SPI to allow different GPIO base/AF for each pin. Adds `DEBUG_UART` support for H7. 2022-12-20 13:31:28 +01:00
David Garske c3b5ac156b Experimental STM32U5 external flash support. 2022-11-23 18:13:03 +01:00
Daniele Lacamera a6fdec3901 self-encrypt prototype; tested on stm32l0 2022-09-21 18:49:52 +02:00
David Garske d38de3b432 Update copyright year 2021-07-19 07:50:02 -07:00
Glenn Ergeerts 4a84fd369e configure GPIO pull-down and speed settings for SPI CLK, MISO and MOSI for STM32L0 2020-11-19 13:51:28 +01:00
Liam 4e823af012 surround faster speed in ifdef so it only gets used for STM32L0 platform 2020-11-05 14:07:24 +01:00
Liam 579871f72e increase spi speed 2020-11-05 14:07:24 +01:00
Daniele Lacamera 533fa9b4a2 Added RAMFUNCTION tag to SPI flash functions 2020-07-06 10:13:52 +02:00
David Garske 2560bdc6d7 Added TPM RSA verify support. Added support for using software SHA-256 hasing with TPM because its much faster. (Note: to use TPM for hashing define `WOLFBOOT_HASH_TPM`). 2020-05-25 08:28:02 -07:00
Chris Conlon 1f57ad9f39 update copyright to 2020 2020-01-03 15:36:00 -08:00
Daniele Lacamera 977b6e8975 Fixed CS pin pullup release 2019-12-23 13:34:24 +01:00
David Garske 00fff87d74 Revert SPIx_CR2 change. 2019-12-20 10:40:56 -08:00
David Garske a342b7824f Minor cleanups. 2019-12-20 10:22:13 -08:00
Daniele Lacamera 2f05d44c95 Fixed SPI defines, fix TPM SHA alignment in header 2019-12-20 19:08:31 +01:00
David Garske 485253f305 Fix build error with macro typo. 2019-12-20 19:08:31 +01:00
Daniele Lacamera 25455744b6 Make Stm32 SPI driver more generic to reuse on other STM32 platforms 2019-12-20 19:08:31 +01:00