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wolfBoot
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103 Commits (a8c8c19fe8ddbf160bb441c4350728b7ea71760c)

Author SHA1 Message Date
David Garske a8c8c19fe8 Add LS1028A eSDHC SD card disk boot support 2026-09-17 12:33:19 +02:00
David Garske b0fe251747 Add Nuvoton NuMaker M2354 Cortex-M23 target with TrustZone 2026-09-14 18:08:40 +02:00
David Garske 24c23e767b Add T1040 eSDHC SD card disk boot support, first big-endian disk-boot target 2026-09-10 08:15:48 +02:00
David Garske 664b09a075 update_disk: load signed image from a file when a filesystem is present 2026-09-02 10:47:33 +02:00
David Garske 4fedc93ed8 imx95_m7: fix console/status overlap, cache handoff, timebase and build wiring 2026-08-24 18:46:41 +02:00
David Garske 88984858d5 Peer review fixes (thanks Jack) 2026-08-24 12:47:34 +02:00
David Garske 71b855f7b5 cm4: add wolfCrypt FIPS 140-3 support + CI, SDHCI unit test, review fixes 2026-08-24 12:47:34 +02:00
David Garske 5c07c3797e zynq: provide hal_get_timer_us for BOOT_BENCHMARK/UPDATE_DISK builds without MMU, avoiding libgcc 128-bit division in the test-app link 2026-08-21 07:17:01 +02:00
David Garske f0ea7fe484 ci: build zynqmp with FIT_RAMDISK to cover the src/fdt.c initrd paths 2026-08-18 11:04:53 +02:00
David Garske 27edd0f5e7 tegra234: bare-metal BL33 target with verified EL2->EL1 + device-tree boot 2026-08-18 11:01:45 +02:00
Daniele Lacamera db8e768bbc aarch64: link the ARM ChaCha port when ChaCha is selected 
Under WOLFSSL_ARMASM, chacha.c calls wc_chacha_crypt_bytes(), which
arch.mk never adds for AArch64 -- it only pulls in the aes/sha ports.
Any AArch64 build using ChaCha failed to link. Add the object in
options.mk, where ChaCha is selected.

Also add a ChaCha variant of the zynqmp_sdcard ENCRYPT build to CI.
 2026-08-11 13:59:06 +02:00
Daniele Lacamera 4726dce42b update_disk: use wc_ForceZero() in the DISK_ENCRYPT helpers 
ForceZero() is only visible in libwolfboot.c, which pulls in misc.c
inline; update_disk.c called it without a declaration, so any config with
disk encryption failed to build. Use the exported wc_ForceZero() from
memory.o instead, which is always linked.

Add a zynqmp_sdcard ENCRYPT build job to CI, the only one that compiles
these paths.
 2026-08-11 13:59:06 +02:00
David Garske 34941079e1 Add aarch64_efi target: wolfBoot as an AArch64 UEFI application 2026-08-10 21:03:50 +02:00
David Garske e718eed709 PolarFire SoC: LPDDR4 DDR init for MPFS250T Video Kit (M-Mode) 2026-08-03 12:27:22 +02:00
Mattia Moffa 3468e965e7 Add MAX32666 CI 2026-07-31 14:33:56 +02:00
David Garske 40e732e57c ci: build Renesas RX example configs 2026-07-30 15:32:31 +02:00
David Garske d66d9b119f zynq: add optional ZynqMP PHY init over GEM MDIO 2026-07-30 15:26:01 +02:00
David Garske 1ceaef3eee zynqmp: wolfBoot ZynqMP FSBL with signed FIT Linux boot and EL3 security (eFuse/PUF/AES-CSU) 2026-07-22 11:56:40 +02:00
Brett Nicholas 235bd820e6 Add support for auxillary algorithms and cert chain/TPM usage 2026-07-22 11:47:16 +02:00
Alex Lanzano 76b023008b Add DEBUG_UART build test for stm32wba. Fix stm32wba clock init 2026-07-02 08:44:45 +02:00
Alex Lanzano 337dabf2f2 Implement port for STM32WBA. Bump wolfHAL lib to latest 2026-07-02 08:44:45 +02:00
Marco Oliverio 723fffebc8 tpm: build MFG identity configs in CI 2026-06-18 11:06:18 +02:00
David Garske 7cdfb4266a NXP T2080 / CW VPX3-152: VxWorks 7 64-bit boot support 
Add wolfBoot support for booting VxWorks 7 SMP 64-bit (and signed ELF
images) on the NXP T2080 (e6500) / Curtiss-Wright VPX3-152.

Key fix: bring up the e6500 cluster L2 cache in the correct order -- set
L2PE (ECC) in its own polled write BEFORE enabling L2E, with L2FI|L2LFC --
matching CW U-Boot (SDK2.0). The previous bare-L2E init left the L2 ECC
array uninitialized for the kernel's 0x1E0000 set, machine-checking VxWorks
(MCSR[IF], L2ERRDET MBECC).

Also: ePAPR spin-table SMP bring-up of all four cores, ELF in-place loader
staging-overlap fix, DPAA/LIODN + QMan/BMan init, 64-bit OS handoff
(LAW/TLB/IVOR), and NAII 68PPC2 + CW VPX3-152 board configs.
 2026-06-15 06:13:28 +02:00
Alex Lanzano 5cb653b141 Remove wolfHAL specific example config 2026-06-10 17:12:25 +02:00
Alex Lanzano 01c52d87e8 remove wolfhal TARGET. Add WOLFHAL option 2026-06-10 17:12:25 +02:00
Alex Lanzano 125872c571 Create STM32WB wolfHAL example. GC sections on all test apps 2026-06-10 17:12:25 +02:00
David Garske c075549ea2 Add wolfBoot support for STM32G4 2026-05-29 13:10:15 +02:00
David Garske 9786f5608b Add wolfBoot port for STM32N6 (NUCLEO-N657X0-Q) 
Co-authored-by: Aidan Garske <aidan@wolfssl.com>
 2026-05-28 16:49:57 +02:00
Yosuke Shimizu f4d5340641 Add hardware-based DICE on mcxn 2026-05-21 20:49:20 +02:00
David Garske b94954eab4 Add Xilinx Zynq-7000 (ZC702) wolfBoot port 2026-05-12 12:06:05 +02:00
David Garske af40ae1471 Add STM32C5 target (NUCLEO-C5A3ZG) 2026-05-06 19:02:58 +02:00
David Garske 980022de13 Add wolfBoot port for STM32U3 (NUCLEO-U385RG-Q) 
New HAL port for the STM32U3 family (Cortex-M33, no TrustZone,
1MB dual-bank flash with 4KB pages, 64-bit double-word writes).

Features:
- hal/stm32u3.c, hal/stm32u3.h, hal/stm32u3.ld: flash driver,
  clock init (96 MHz MSIRC0 via EPOD booster), inline UART, ICACHE
- config/examples/stm32u3.config: ECC384/SHA384, DEBUG_UART=1,
  NVM_FLASH_WRITEONCE=1, RAM_CODE=1, dual-bank layout
- test-app/app_stm32u3.c: LED blink + UART output + version check
- tools/scripts/prepare_update_u3.sh: v2 pBOOT update image builder
- docs/Targets.md: STM32U3 section with build/flash/update instructions
- CI: stm32u3_test job + Clang rebuild coverage

Tested on NUCLEO-U385RG-Q:
- Verified boot with ECC384/SHA384 signature
- 96 MHz clock (MSIRC0 + SMPS + EPOD booster + VOS1)
- UART output on USART1 PA9/PA10 (ST-LINK VCP)
- TEST_FLASH erase/write/readback on both flash banks
- A/B firmware update (v1 -> v2 swap with pBOOT trigger)
 2026-04-27 17:00:41 +02:00
David Garske 00313b3e43 Rename LPC54S018M to LPC54S0XX 2026-04-22 14:10:55 +02:00
David Garske eee953f823 Add tests and improve docs 2026-04-22 14:10:55 +02:00
Daniele Lacamera 4ffa24c05f Update CI + fix new findings with cppcheck 2.20 2026-03-24 12:19:44 +01:00
Mattia Moffa 558b6584ec Add GitHub workflows 2026-03-18 22:32:09 +01:00
Thomas Cook 9fecc9c3b7 Add .github workflow build tests 2026-03-18 11:53:26 +01:00
Mattia Moffa 1ab85fe576 Add github workflow 2026-03-18 09:15:00 +01:00
David Garske d23943a5af PolarFire SoC M-Mode, QSPI and L2-LIM support 
Adds support for running wolfBoot in **Machine Mode (M-mode)** on the PolarFire SoC MPFS250T, booting from eNVM and loading a signed application from **SC QSPI flash** into on-chip LIM (Loosely Integrated Memory). No HSS (Hart Software Services) or DDR is required. It also extends the existing PolarFire HAL with multi-hart support, L2 cache configuration, per-hart UART, and refactors shared code (SDHCI, SCB mailbox, linker/test-app) for both S-mode and M-mode builds.
 2026-03-09 07:29:27 +01:00
David Garske a5356b830a NXP T2080 Port Refresh 
* Initial port refresh for the NXP T2080 target
* IFC Flash driver and multi-core support on T2080
* Working wolfBoot test-app startup on T2080
* Support for NAII and Curtiss-Wright T2080 vendor boards
 2026-03-05 17:49:37 +01:00
David Garske 88a32de298 Move .bif and add CI test 2026-03-05 10:12:02 +01:00
Mattia Moffa e2a74ba09d Replace non-existing boards 2026-01-30 01:59:15 +01:00
Mattia Moffa 9823c55221 Restore Kinetis GitHub Workflows 2026-01-30 01:08:55 +01:00
Mattia Moffa fed7eec0ad Update MCUXpresso SDK for iMX-RT too 2026-01-30 01:07:13 +01:00
Mattia Moffa 233abfe979 Fix LPC54 github workflow 2026-01-29 17:55:33 +01:00
Mattia Moffa 109dbd08d9 Update MCUXpresso SDK to new refactor 
Updates targets using the deprecated
https://github.com/nxp-mcuxpresso/legacy-mcux-sdk to use
https://github.com/nxp-mcuxpresso/mcuxsdk-manifests instead.
 2026-01-29 17:35:24 +01:00
David Garske 810be2d576
Merge pull request #671 from mattia-moffa/20260107-mcxn 
NXP MCXN non-TrustZone + TrustZone port
 2026-01-26 09:28:14 -08:00
David Garske ee3c313a66 Versal port cleanups 2026-01-26 13:08:50 +01:00
Mattia Moffa b1528bacb4 Add board name to github workflows 2026-01-22 23:34:06 +01:00
Mattia Moffa 8c00a73cc8 Add GitHub workflows 2026-01-22 18:57:00 +01:00